Anne-Johan Annema

According to our database1, Anne-Johan Annema authored at least 37 papers between 1994 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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Online presence:

On csauthors.net:

Bibliography

2020
Theory and Implementation of a Load-Mismatch Protective Class-E PA System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Colpitts-Based Frequency Reference Achieving a Single-Trim ± 120ppm Accuracy from -50 to 170°C.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A Delay Spread Cancelling Waveform Characterizer for RF Power Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement.
IEEE J. Solid State Circuits, 2018

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.
IEEE J. Solid State Circuits, 2018

Augmentation of Class-E PA Reliability under Load Mismatch Conditions.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Hardware Implementation Overhead of Switchable Matching Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 30fJ/comparison dynamic bias comparator.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Random Telegraph Signal phenomena in avalanche mode diodes: Application to SPADs.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
On the Minimum Number of States for Switchable Matching Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An Interleaved Full Nyquist High-Speed DAC Technique.
IEEE J. Solid State Circuits, 2015

2014
A 110mW, 0.04mm<sup>2</sup>, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance.
IEEE J. Solid State Circuits, 2013

A Wideband IM3 Cancellation Technique for CMOS Π- and T-Attenuators.
IEEE J. Solid State Circuits, 2013

2012
RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A wideband IM3 cancellation technique for CMOS attenuators.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 0.0025mm<sup>2</sup> bandgap voltage reference for 1.1V supply in standard 0.16μm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based Design.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Noise and Nonlinearity Modeling of Active Mixers for Fast and Accurate Estimation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2009
A sub-1V bandgap voltage reference in 32nm FinFET technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A multi-step P-cell for LNA design automation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A general weak nonlinearity model for LNAs.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Analytical Design Equations for Class-E Power Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Generalized Analytical Design Equations for Variable Slope Class-E Power Amplifiers.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Bandwidth of integrated photodiodes in standard CMOS for CD/DVD applications.
Microelectron. Reliab., 2005

2004
Reducing quantization noise with recursive Sigma Delta modulators.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

1995
Analog weight adaptation hardware.
Neural Process. Lett., 1995

Feed-forward neural networks - vector decomposition analysis, modelling and analog implementation.
The Kluwer international series in engineering and computer science 314, Kluwer, ISBN: 978-0-7923-9567-6, 1995

1994
Learning behavior and temporary minima of two-layer neural networks.
Neural Networks, 1994


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