Daniël Schinkel

Orcid: 0000-0002-7886-3979

According to our database1, Daniël Schinkel authored at least 17 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
Compensating Processing Delay in Excess of One Clock Cycle in Noise Shaping Loops Without Altering the Filter Topology.
IEEE Access, 2021

2020
EMI Reduction in Class-D Amplifiers by Actively Reducing PWM Ripple.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2018
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.
IEEE J. Solid State Circuits, 2018

2017
A Multiphase Class-D Automotive Audio Amplifier With Integrated Low-Latency ADCs for Digitized Feedback After the Output Filter.
IEEE J. Solid State Circuits, 2017

5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
15.3 A 115dB-DR audio DAC with -61dBFS out-of-band noise.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2010
Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects.
IEEE J. Solid State Circuits, 2010

A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s.
IEEE J. Solid State Circuits, 2010

2009
Low-Power, High-Speed Transceivers for Network-on-Chip Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Optimal Positions of Twists in Global On-Chip Differential Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects.
IEEE J. Solid State Circuits, 2006

2005
Optimally-placed twists in global on-chip differential interconnects.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

An audio FIR-DAC in a BCD process for high power class-D amplifiers.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
Reducing quantization noise with recursive Sigma Delta modulators.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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