Hans G. Kerkhoff

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020

On-Chip Embedded Instruments Data Fusion and Life-Time Prognostics of Dependable VLSI-SoCs using Machine-Learning.

[BibT_eX]

[DOI]

Leila Bagheriye

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Life-Time Prognostics of Dependable VLSI-SoCs using Machine-learning.

[BibT_eX]

[DOI]

Leila Bagheriye

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

A New Monitor Insertion Algorithm for Intermittent Fault Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

On-chip EOL Prognostics Using Data-Fusion of Embedded Instruments for Dependable MP-SoCs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at Board Level.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

Efficient Structured Scan Patterns Retargeting for Hierarchical IEEE 1687 Networks.

[BibT_eX]

[DOI]

M. Watheq El-Kharashi

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin American Test Symposium, 2019

DARS: An EDA Framework for Reliability and Functional Safety Management of System-on-Chips.

[BibT_eX]

[DOI]

Ahmed M. Y. Ibrahim

Proceedings of the IEEE International Test Conference, 2019

An On-Chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips.

[BibT_eX]

[DOI]

Ahmed M. Y. Ibrahim

Proceedings of the IEEE International Test Conference in Asia, 2019

IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE European Test Symposium, 2019

Analog Test Interface for IEEE 1687 Employing Split SAR Architecture to Support Embedded Instrument Dependability Applications.

[BibT_eX]

[DOI]

Leon van de Logt

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018

On-Chip Lifetime Prediction for Dependable Many-Processor SoCs Based on Data Fusion.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

IJTAG compatible analogue embedded instruments for MPSoC life-time prediction.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Design and implementation of a dependable CPSoC for automotive applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Industrial Cyber-Physical Systems, 2018

Intermittent Resistance Fault Detection at Board Level.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Enhancing Physical Unclonable Function Robustness Employing Embedded Instruments.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Structured scan patterns retargeting for dynamic instruments access.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

A dependable AMR sensor system for automotive applications.

[BibT_eX]

[DOI]

Proceedings of the International Test Conference in Asia, 2017

An automotive MP-SoC featuring an advanced embedded instrument infrastructure for high dependability.

[BibT_eX]

[DOI]

Proceedings of the International Test Conference in Asia, 2017

A cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Improving the dependability of AMR sensors used in automotive applications.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE European Test Symposium, 2017

BASTION: Board and SoC test instrumentation for ageing and no failure found.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Investigation of Intermittent Resistive Faults in Digital CMOS Circuits.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

Thermal issues in test: An overview of the significant aspects and industrial practice.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Online digital compensation Method for AMR sensors.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

A software framework to calculate local temperatures in CMOS processors.

[BibT_eX]

[DOI]

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Online monitoring of the maximum angle error in AMR sensors.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Towards an automated and reusable in-field self-test solution for MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Microelectronics, 2016

Accessing on-chip temperature health monitors using the IEEE 1687 standard.

[BibT_eX]

[DOI]

Ahmed Badawy

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Designing reliable cyber-physical systems overview associated to the special session at FDL'16.

[BibT_eX]

[DOI]

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Analysis and design of an on-chip retargeting engine for IEEE 1687 networks.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Testing for Intermittent Resistive Faults in CMOS Integrated Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Efficient utilization of hierarchical iJTAG networks for interrupts management.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Detecting intermittent resistive faults in digital CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Highly Dependable Multi-processor SoCs Employing Lifetime Prediction Based on Health Monitors.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Embedded instruments for enhancing dependability of analogue and mixed-signal IPs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Fault-tolerant system for catastrophic faults in AMR sensors.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

On the maximization of the sustained switching activity in a processor.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Online digital offset voltage compensation method for AMR sensors.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

New drain current model for nano-meter MOS transistors on-chip threshold voltage test.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

Application of functional IDDQ testing in a VLIW processor towards detection of aging degradation.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor.

[BibT_eX]

[DOI]

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Intermittent Resistive Faults in Digital CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

Day 1: Invited talk 2: Dependable mixed-signal integrated systems under aging.

[BibT_eX]

[DOI]

Proceedings of the 9th International Design and Test Symposium, 2014

iJTAG integration of complex digital embedded instruments.

[BibT_eX]

[DOI]

Proceedings of the 9th International Design and Test Symposium, 2014

Two soft-error mitigation techniques for functional units of DSP processors.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Linking aging measurements of health-monitors and specifications for multi-processor SoCs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Design of an Embedded Health Monitoring Infrastructure for Accessing Multi-processor SoC Degradation.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

An embedded offset and gain instrument for OpAmp IPs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Rapid transient fault insertion in large digital systems.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

Exploiting Multiple Mahalanobis Distance Metrics to Screen Outliers From Analog Product Manufacturing Test Responses.

[BibT_eX]

[DOI]

Shaji Krishnan

IEEE Des. Test, 2013

Pulse-length determination techniques in the rectangular single event transient fault model.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

An arbitrary stressed NBTI compact model for analog/mixed-signal reliability simulations.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Power-dissipation comparison of two dependability approaches for multi-processor systems.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

Monitoring operating temperature and supply voltage in achieving high system dependability.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

The Essence of Reliability Estimation during Operational Life for Achieving High System Dependability.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Analysing degradation effects in charge-redistribution SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

An indirect technique for estimating reliability of analog and mixed-signal systems during operational life.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

A robust metric for screening outliers from analogue product manufacturing tests responses.

[BibT_eX]

[DOI]

Shaji Krishnan

Proceedings of the 17th IEEE European Test Symposium, 2012

Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based Design.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

An on-line soft error mitigation technique for control logic of VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

The design of dependable flexible multi-sensory System-on-Chips for security applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Monitoring active filters under automotive aging scenarios with embedded instrument.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

A Dependability Solution for Homogeneous MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011

Boosted gain programmable Opamp with embedded gain monitor for dependable SoCs.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

Study of the effects of SET induced faults on submicron technologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011

A Technique for Accelerating Injection of Transient Faults in Complex SoCs.

[BibT_eX]

[DOI]

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

SoC Mixed-Signal Dependability Enhancement: A Strategy from Design to End-of-Life.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

A system-level platform for dependability enhancement and its analysis for mixed-signal SoCs.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

On-line dependability enhancement of multiprocessor SoCs by resource management.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism.

[BibT_eX]

[DOI]

Bart Vermeulen

Proceedings of the 15th European Test Symposium, 2010

Predicting dynamic specifications of ADCs with a low-quality digital input signal.

[BibT_eX]

[DOI]

Xiaoqin Sheng

Vincent Kerzerho

Proceedings of the 15th European Test Symposium, 2010

Multivariate model for test response analysis.

[BibT_eX]

[DOI]

Shaji Krishnan

Proceedings of the 15th European Test Symposium, 2010

On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism.

[BibT_eX]

[DOI]

Bart Vermeulen

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor.

[BibT_eX]

[DOI]

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Block-level bayesian diagnosis of analogue electronic circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

The Test Ability of an Adaptive Pulse Wave for ADC Testing.

[BibT_eX]

[DOI]

Xiaoqin Sheng

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Fault co-simulation for test evaluation of heterogeneous integrated biological systems.

[BibT_eX]

[DOI]

Microelectron. J., 2009

Algorithms for ADC Multi-site Test with Digital Input Stimulus.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE European Test Symposium, 2009

Design of a Highly Dependable Beamforming Chip.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

A Dependable Micro-Electronic Peptide Synthesizer Using Electrode Data.

[BibT_eX]

[DOI]

VLSI Design, 2008

Built-in-Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming Applications.

[BibT_eX]

[DOI]

Oscar Kuiken

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications.

[BibT_eX]

[DOI]

Jarkko J. M. Huijts

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007

Testing Microelectronic Biofluidic Systems.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

2006

Fault Modelling and Co-Simulation in FlowFET-Based Biological Array Systems.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005

The test search for true mixed-signal cores.

[BibT_eX]

[DOI]

Microelectron. J., 2005

Testing of MEMS-based microsystems.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

2004

Scan Test Strategy for Asynchronous-Synchronous Interfaces.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

Testability Issues in Superconductor Electronic.

[BibT_eX]

[DOI]

Arun A. Joseph

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003

Testability-analysis driven test-generation of analogue cores.

[BibT_eX]

[DOI]

M. Stancic

Microelectron. J., 2003

Analog and mixed signal test techniques for SoCs.

[BibT_eX]

[DOI]

Bozena Kaminska

Microelectron. J., 2003

Synchronous Full-Scan for Asynchronous Handshake Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Fast Fault Simulation for Nonlinear Analog Circuits.

[BibT_eX]

[DOI]

Nur Engin

IEEE Des. Test Comput., 2003

Testable Design and Testing of Micro-Electro-Fluidic Arrays.

[BibT_eX]

[DOI]

Mustafa Acar

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Towards Structural Testing of Superconductor Electronics.

[BibT_eX]

[DOI]

Arun A. Joseph

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Enhanced P1500 compliant wrapper suitable for delay fault testing of embedded cores.

[BibT_eX]

[DOI]

H. J. Vermaak

Proceedings of the 8th European Test Workshop, 2003

Scan test strategy for asynchronous-synchronous interfaces [SoC testing].

[BibT_eX]

[DOI]

Proceedings of the 8th European Test Workshop, 2003

2002

An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures.

[BibT_eX]

[DOI]

V. A. Zivkovic

J. Electron. Test., 2002

SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow?

[BibT_eX]

[DOI]

Salvador Mir

H. Bederr

R. D. (Shawn) Blanton

H. J. Klim

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A New Test Generation Approach for Embedded Analogue Cores in SoC.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Automatic Scan Insertion and Test Generation for Asynchronous Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Testable Design and Testing of High-Speed Superconductor Microelectronics.

[BibT_eX]

[DOI]

Arun A. Joseph

Sander Heuvelmans

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Testing of a microanalysis system.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2001

Design for Delay Testability in High-Speed Digital ICs.

[BibT_eX]

[DOI]

J. Electron. Test., 2001

Fault Modeling and Fault Simulation in Mixed Micro-Fluidic Microelectronic Systems.

[BibT_eX]

[DOI]

Hans P. A. Hendriks

J. Electron. Test., 2001

Modeling a Verification Test System for Mixed-Signal Circuits.

[BibT_eX]

[DOI]

David San Segundo Bello

IEEE Des. Test Comput., 2001

Tackling test trade-offs from design, manufacturing to market using economic modeling.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Increasing the Fault Coverage in Multiple Clock Domain Systems by Using On-Line Testing of Synchronizers.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations.

[BibT_eX]

[DOI]

Herman J. Vermaak

Proceedings of the 6th European Test Workshop, 2001

Reducing analogue fault-simulation time by using high-level modelling in dotss for an industrial design.

[BibT_eX]

[DOI]

Liquan Fang

Guido Gronthoud

Proceedings of the 6th European Test Workshop, 2001

2000

A Low-Speed BIST Framework for High-Performance Circuit Testing.

[BibT_eX]

[DOI]

Mansour Shashaani

Manoj Sachdev

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Bridging the testing speed gap: design for delay testability.

[BibT_eX]

[DOI]

Proceedings of the 5th European Test Workshop, 2000

Design and Test Space Exploration of Transport-Triggered Architectures.

[BibT_eX]

[DOI]

V. A. Zivkovic

Proceedings of the 2000 Design, 2000

1999

Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters.

[BibT_eX]

[DOI]

Richard Rosing

Manoj Sachdev

J. Electron. Test., 1999

Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach.

[BibT_eX]

[DOI]

Chris Feige

Jan Ten Pierick

Clemens Wouters

J. Electron. Test., 1999

Integrated Design and Test of Mixed-Signal Circuits.

[BibT_eX]

[DOI]

Nur Engin

Han Speek

J. Electron. Test., 1999

Configurations for IDDQ-Testable PLAs.

[BibT_eX]

[DOI]

Manoj Sachdev

IEEE Des. Test Comput., 1999

1998

Microsystem Testing: Challenge or Common Knowledge?

[BibT_eX]

[DOI]

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Smart sensor system application: an integrated compass.

[BibT_eX]

[DOI]

G. Diemel

Proceedings of the European Design and Test Conference, 1997

Compact structural test generation for analog macros.

[BibT_eX]

[DOI]

V. Kaal

Proceedings of the European Design and Test Conference, 1997

1996

MISMATCH: a basis for semi-automatic functional mixed-signal test-pattern generation.

[BibT_eX]

[DOI]

Han Speek

Nur Engin

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Test Structures on MCM Active Substrate: Is it worthwhile?

[BibT_eX]

[DOI]

Joan Oliver

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Gate delay fault test generation for non-scan circuits.

[BibT_eX]

[DOI]

G. Van Brakel

Uwe Gläser

Heinrich Theodor Vierhaus

Proceedings of the 1995 European Design and Test Conference, 1995

1992

A fast and accurate characterization method for full-CMOS circuits.

[BibT_eX]

[DOI]

Rafael Peset Llopis

Proceedings of the conference on European design automation, 1992

1991

A design-for-testability expert system for silicon compilers.

[BibT_eX]

[DOI]

R. P. van Riessen

J. M. J. Janssen

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

A performance analysis tool for performance-driven micro-cell generation.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1991

1990

Testability analysis of analog systems.

[BibT_eX]

[DOI]

Gertjan J. Hemink

Berend W. Meijer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Designing and Implementing an Architecture with Boundary Scan.

[BibT_eX]

[DOI]

R. P. van Riessen

A. Kloppenburg

IEEE Des. Test Comput., 1990

A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach.

[BibT_eX]

[DOI]

Jon T. Butler

Siep Onneweer

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

1988

Multiple-Valued CCD Circuits.

[BibT_eX]

[DOI]

Jon T. Butler

Computer, 1988

TASTE: A Tool for Analog System Testability Evaluation.

[BibT_eX]

[DOI]

Gertjan J. Hemink

Berend W. Meijer

Proceedings of the Proceedings International Test Conference 1988, 1988

1981

Multiple-Valued Logic Charge-Coupled Devices.

[BibT_eX]

[DOI]