Apala Guha

According to our database1, Apala Guha authored at least 18 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Deepframe: A Profile-Driven Compiler for Spatial Hardware Accelerators.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
TAPAS: Generating Parallel Accelerators from Parallel Programs.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

2017
DFGenTool: A Dataflow Graph Generation Tool for Coarse Grain Reconfigurable Architectures.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

The interaction of last-level-cache mechanisms on modern processors.
Proceedings of the International Symposium on Memory Systems, 2017

The Impact of Toxic Language on the Health of Reddit Communities.
Proceedings of the Advances in Artificial Intelligence, 2017

2016
Chainsaw: Von-neumann accelerators to leverage fused instruction chains.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Easy and expressive LLC contention model.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

On the applicability of simple cache models for modern processors.
Proceedings of the 2nd International Conference on Green High Performance Computing, 2016

2013
Systematic evaluation of workload clustering for extremely energy-efficient architectures.
SIGARCH Computer Architecture News, 2013

Exascale workload characterization and architecture implications.
Proceedings of the 2013 Spring Simulation Multiconference, SpringSim '13, 2013

2012
Memory optimization of dynamic binary translators for embedded systems.
TACO, 2012

Poster: An Exascale Workload Study.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Abstract: An Exascale Workload Study.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

2010
DBT path selection for holistic memory efficiency and performance.
Proceedings of the 6th International Conference on Virtual Execution Environments, 2010

Balancing memory and performance through selective flushing of software code caches.
Proceedings of the 2010 International Conference on Compilers, 2010

2007
Virtual Execution Environments: Support and Tools.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Reducing Exit Stub Memory Consumption in Code Caches.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007


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