Alexander Fell

According to our database1, Alexander Fell authored at least 17 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2020
Symmetric $k$-Means for Deep Neural Network Compression and Hardware Acceleration on FPGAs.
IEEE J. Sel. Top. Signal Process., 2020

2019
TAD: time side-channel attack defense of obfuscated source code.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
CIDPro: Custom Instructions for Dynamic Program Diversification.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
DFGenTool: A Dataflow Graph Generation Tool for Coarse Grain Reconfigurable Architectures.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Automated, inter-macro channel space adjustment and optimization for faster design closure.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A Parallel Architecture for High Frame Rate Stereo using Semi-Global Matching.
Proceedings of the British Machine Vision Conference 2017, 2017

2015
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2014
Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2009
REDEFINE: Runtime reconfigurable polymorphic ASIC.
ACM Trans. Embed. Comput. Syst., 2009

Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.
Proceedings of the 2009 International Conference on Compilers, 2009

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Synthesis of application accelerators on Runtime Reconfigurable Hardware.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008


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