Gilles Pokam

Orcid: 0009-0002-4363-5383

According to our database1, Gilles Pokam authored at least 48 papers between 2004 and 2023.

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Bibliography

2023
Online Code Layout Optimizations via OCOLOS.
IEEE Micro, 2023

EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction Caching.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2022
OCOLOS: Online COde Layout OptimizationS.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021
DMon: Efficient Detection and Correction of Data Locality Problems Using Selective Profiling.
Proceedings of the 15th USENIX Symposium on Operating Systems Design and Implementation, 2021

Twig: Profile-Guided BTB Prefetching for Data Center Applications.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
I-SPY: Context-Driven Conditional Instruction Prefetching with Coalescing.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

CHiRP: Control-Flow History Reuse Prediction.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Hurdle: Securing Jump Instructions Against Code Reuse Attacks.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Huron: hybrid false sharing detection and repair.
Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019

2018
TAPAS: Generating Parallel Accelerators from Parallel Programs.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Architectural support for convolutional neural networks on modern CPUs.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017
TMI: thread memory isolation for false sharing repair.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

AsyncClock: Scalable Inference of Asynchronous Event Causality.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016
Remix: online detection and repair of cache contention for the JVM.
Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2016

LASER: Light, Accurate Sharing dEtection and Repair.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

POSTER: Fault-tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Failure sketching: a technique for automated root cause diagnosis of in-production failures.
Proceedings of the 25th Symposium on Operating Systems Principles, 2015

Failure Sketches: A Better Way to Debug.
Proceedings of the 15th Workshop on Hot Topics in Operating Systems, 2015

TSXProf: Profiling Hardware Transactions.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
Race detection for event-driven mobile applications.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2014

Invyswell: a hybrid transactional memory for haswell's restricted transactional memory.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Selective mutation testing for concurrent code.
Proceedings of the International Symposium on Software Testing and Analysis, 2013

QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

But How Do We Really Debug Transactional Memory Programs?
Proceedings of the 5th USENIX Workshop on Hot Topics in Parallelism, 2013

Cyrus: unintrusive application-level record-replay for replay parallelism.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

Concurrent predicates: A debugging technique for every parallel programmer.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Maple: a coverage-driven testing tool for multithreaded programs.
Proceedings of the 27th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2012

Visualizing transactional memory.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
CoreRacer: a practical memory race recorder for multicore x86 TSO processors.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

RADBench: A Concurrency Bug Benchmark Suite.
Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism, 2011

The Case for Message Passing on Many-Core Chips.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2009
An analytic framework for performance modeling of software transactional memory.
Comput. Networks, 2009

Modeling software transactional memory with AnyLogic.
Proceedings of the 2nd International Conference on Simulation Tools and Techniques for Communications, 2009

Architecting a chunk-based memory race recorder in modern CMPs.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

An analytic model of optimistic Software Transactional Memory.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

An Analytic Model for Optimistic STM with Lazy Locking.
Proceedings of the Analytical and Stochastic Modeling Techniques and Applications, 2009

2006
A case for a complexity-effective, width-partitioned microarchitecture.
ACM Trans. Archit. Code Optim., 2006

BugNet: Recording Application-Level Execution for Deterministic Replay Debugging.
IEEE Micro, 2006

Unbounded page-based transactional memory.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004
SWARP: a retargetable preprocessor for multimedia instructions.
Concurr. Comput. Pract. Exp., 2004

Speculative software management of datapath-width for energy optimization.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

An Offline Approach for Whole-Program Paths Analysis Using Suffix Arrays.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

Energy-Efficiency Potential of a Phase-Based Cache Resizing Scheme for Embedded Systems.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004


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