Ashok Jagannathan

According to our database, Ashok Jagannathan authored at least 11 papers between 1999 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Cost and Communication-Aware Fast Placement of Processing Elements in Chiplets for 2.5D Systems.

Ayman Un Nisa, Ashok Jagannathan, Sumit K. Mandal

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2017

ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks.

Swagath Venkataramani, Ashish Ranjan, Subarno Banerjee, Dipankar Das, Sasikanth Avancha, Ashok Jagannathan, Ajaya Durg, Dheemanth Nagaraj, Bharat Kaul, Pradeep Dubey, Anand Raghunathan

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2014

Array scalarization in high level synthesis.

Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2007

Accelerating Sequential Applications on CMPs Using Core Spilling.

Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski

IEEE Trans. Parallel Distributed Syst., 2007

2006

An automated design flow for 3D microarchitecture evaluation.

Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Understanding the energy efficiency of SMT and CMP with multiclustering.

Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Instruction set extension with shadow registers for configurable processors.

Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Microarchitecture evaluation with floorplanning and interconnect pipelining.

Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003

Microarchitecture evaluation with physical planning.

Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis

Proceedings of the 40th Design Automation Conference, 2003

2000

A fast algorithm for context-aware buffer insertion.

Ashok Jagannathan, Sung-Woo Hur, John Lillis

Proceedings of the 37th Conference on Design Automation, 2000

1999

Timing driven maze routing.

Sung-Woo Hur, Ashok Jagannathan, John Lillis

Proceedings of the 1999 International Symposium on Physical Design, 1999