Glenn Reinman

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

CHARM: a composable heterogeneous accelerator-rich microprocessor.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Static and dynamic co-optimizations for blocks mapping in hybrid caches.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Architecture support for accelerator-rich CMPs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Compilation and architecture support for customized vector instruction extension.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Footstep navigation for dynamic crowds.

[BibT_eX]

[DOI]

Comput. Animat. Virtual Worlds, 2011

Customizable Domain-Specific Computing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

A Behavior-Authoring Framework for Multiactor Simulations.

[BibT_eX]

[DOI]

IEEE Computer Graphics and Applications, 2011

A modular framework for adaptive agent-based steering.

[BibT_eX]

[DOI]

Proceedings of the Symposium on Interactive 3D Graphics and Games, 2011

Behavior authoring for crowd simulations.

[BibT_eX]

[DOI]

Proceedings of the Symposium on Interactive 3D Graphics and Games, 2011

Scenario Space: Characterizing Coverage, Quality, and Failure of SteeringAlgorithms.

[BibT_eX]

[DOI]

Proceedings of the 2011 Eurographics/ACM SIGGRAPH Symposium on Computer Animation, 2011

Improved Benchmarking for Steering Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Motion in Games - 4th International Conference, 2011

An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

An energy-efficient adaptive hybrid cache.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

The DIMM tree architecture: A high bandwidth and scalable memory system.

[BibT_eX]

[DOI]

Kanit Therdsteerasukdi

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support.

[BibT_eX]

[DOI]

Yu-Ting Chen

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Accelerating vision and navigation applications on a customizable platform.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

RF-Interconnect for Future Network-On-Chip.

[BibT_eX]

[DOI]

Sai-Wang Tam

Eran Socher

Glenn D. Reinman

Proceedings of the Low Power Networks-on-Chip., 2011

2010

ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip.

[BibT_eX]

[DOI]

Chunyue Liu

Proceedings of the 47th Design Automation Conference, 2010

2009

Fool me twice: Exploring and exploiting error tolerance in physics-based animation.

[BibT_eX]

[DOI]

ACM Trans. Graph., 2009

SteerBench: a benchmark suite for evaluating steering behaviors.

[BibT_eX]

[DOI]

Comput. Animat. Virtual Worlds, 2009

Multiband RF-interconnect for reconfigurable network-on-chip communications.

[BibT_eX]

[DOI]

Sai-Wang Tam

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

SteerBug: an interactive framework for specifying and detecting steering behaviors.

[BibT_eX]

[DOI]

Proceedings of the 2009 ACM SIGGRAPH/Eurographics Symposium on Computer Animation, 2009

A scalable micro wireless interconnect structure for CMPs.

[BibT_eX]

[DOI]

Proceedings of the 15th Annual International Conference on Mobile Computing and Networking, 2009

An Open Framework for Developing, Evaluating, and Sharing Steering Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Motion in Games, Second International Workshop, 2009

2008

Investigating the effects of fine-grain three-dimensional integration on microarchitecture design.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2008

Watch Out! A Framework for Evaluating Steering Behaviors.

[BibT_eX]

[DOI]

Proceedings of the Motion in Games, First International Workshop, 2008

Power reduction of CMP communication networks via RF-interconnects.

[BibT_eX]

[DOI]

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

RF interconnects for communications on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

MC-Sim: an efficient simulation tool for MPSoC designs.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

CMP network-on-chip overlaid with multi-band RF-interconnect.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007

Accelerating Sequential Applications on CMPs Using Core Spilling.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2007

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

ParallAX: an architecture for real-time physics.

[BibT_eX]

[DOI]

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Fine grain 3D integration for microarchitecture design through cube packing exploration.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

An Evaluation of Deeply Decoupled Cores.

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2006

Enabling real-time physics simulation in future interactive entertainment.

[BibT_eX]

[DOI]

Thomas Y. Yeh

Petros Faloutsos

Proceedings of the 2006 ACM SIGGRAPH symposium on Videogames, 2006

Handheld System Energy Reduction by OS-Driven Refresh.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Improving the performance and power efficiency of shared helpers in CMPs.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Compilers, 2006

An automated design flow for 3D microarchitecture evaluation.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Dynamically configurable shared CMP helper engines for improved performance.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2005

Precise Instruction Scheduling.

[BibT_eX]

[DOI]

William H. Mangione-Smith

J. Instr. Level Parallelism, 2005

Understanding the energy efficiency of SMT and CMP with multiclustering.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Tornado warning: the perils of selective replay in multithreaded processors.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual International Conference on Supercomputing, 2005

Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Reducing the Energy of Speculative Instruction Schedulers.

[BibT_eX]

[DOI]

Yongxiang Liu

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Instruction set extension with shadow registers for configurable processors.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Fast and fair: data-stream quality of service.

[BibT_eX]

[DOI]

Thomas Y. Yeh

Proceedings of the 2005 International Conference on Compilers, 2005

Microarchitecture evaluation with floorplanning and interconnect pipelining.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Using a serial cache for energy efficient instruction fetching.

[BibT_eX]

[DOI]

J. Syst. Archit., 2004

Low-Overhead Core Swapping for Thermal Management.

[BibT_eX]

[DOI]

Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Scaling the issue window with look-ahead latency prediction.

[BibT_eX]

[DOI]

Proceedings of the 18th Annual International Conference on Supercomputing, 2004

2003

Reducing energy and delay using efficient victim caches.

[BibT_eX]

[DOI]

William H. Mangione-Smith

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Just Say No: Benefits of Early Cache Miss Determinatio.

[BibT_eX]

[DOI]

William H. Mangione-Smith

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Microarchitecture evaluation with physical planning.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

High Performance and Energy Efficient Serial Prefetch Architecture.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 4th International Symposium, 2002

2001

Optimizations Enabled by a Decoupled Front-End Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

2000

A Comparative Survey of Load Speculation Architectures.

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2000

1999

Fetch Directed Instruction Prefetching.

[BibT_eX]

[DOI]

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

A Scalable Front-End Architecture for Fast Instruction Delivery.

[BibT_eX]

[DOI]

Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Selective Value Prediction.

[BibT_eX]

[DOI]

Dean M. Tullsen

Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Classifying load and store instructions for memory renaming.

[BibT_eX]

[DOI]

Proceedings of the 13th international conference on Supercomputing, 1999

1998

Predictive Techniques for Aggressive Load Speculation.

[BibT_eX]

[DOI]