Hannah Honghua Yang

According to our database1, Hannah Honghua Yang authored at least 31 papers between 1991 and 2016.

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Bibliography

2016
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach.
Encyclopedia of Algorithms, 2016

2008
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

2007
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

2006
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.
ACM Trans. Design Autom. Electr. Syst., 2006

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.
IEEE Trans. on Circuits and Systems, 2006

Integrating dynamic thermal via planning with 3D floorplanning algorithm.
Proceedings of the 2006 International Symposium on Physical Design, 2006

2005
A Theoretical Upper Bound for IP-Based Floorplanning.
Proceedings of the Computing and Combinatorics, 11th Annual International Conference, 2005

Microarchitecture evaluation with floorplanning and interconnect pipelining.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Constrained floorplanning using network flows.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Integrated floorplanning with buffer/channel insertion for bus-based designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Constrained "Modern" Floorplanning.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Multilevel floorplanning/placement for large-scale modules using B*-trees.
Proceedings of the 40th Design Automation Conference, 2003

2002
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.
Proceedings of 2002 International Symposium on Physical Design, 2002

2001
On extending slicing floorplan to handle L/T-shaped modules andabutment constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Faster and more accurate wiring evaluation in interconnect-centric floorplanning.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000
Slicing floorplans with range constraint.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

1999
Slicing floorplans with boundary constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Logic Verification of Very Large Circuits Using Shark.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Integrated floorplanning and interconnect planning.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Optimal min-area min-cut replication in partitioned circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

1997
Circuit clustering for delay minimization under area and pin constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

An Efficient Parallel Algorithm for the Layered Planar Monotone Circuit Value Problem.
Algorithmica, 1997

1996
Balanced partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

An Efficient Parallel Algorithm for the General Planar Monotone Circuit Value Problem.
SIAM J. Comput., 1996

1995
New algorithms for min-cut replication in partitioned circuits.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
Finding the Closed Partition of a Planar Graph.
Algorithmica, 1994

Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Efficient network flow based min-cut balanced partitioning.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1991
An NC algorithm for the general planar monotone circuit value problem.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991


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