Jeff Zhang
Orcid: 0000-0001-7411-8923Affiliations:
- Arizona State University, AZ, USA
- Harvard University, Cambridge, MA, USA (former)
- New York University, NY, USA (former)
According to our database1,
Jeff Zhang
authored at least 37 papers
between 2015 and 2024.
Collaborative distances:
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Bibliography
2024
ACM Trans. Sens. Networks, March, 2024
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
COFFEE: Cross-Layer Optimization for Fast and Efficient Executions of Sinkhorn-Knopp Algorithm on HPC Systems.
IEEE Trans. Parallel Distributed Syst., July, 2023
Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis.
CoRR, 2023
A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE International Conference on Robotics and Automation, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
IEEE Trans. Computers, 2022
IEEE Open J. Commun. Soc., 2022
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
M2M-Routing: Environmental Adaptive Multi-agent Reinforcement Learning based Multi-hop Routing Policy for Self-Powered IoT Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
CoRR, 2021
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
RecPipe: Co-designing Models and Hardware to Jointly Optimize Recommendation Quality and Performance.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
SAC: A Novel Multi-hop Routing Policy in Hybrid Distributed IoT System based on Multi-agent Reinforcement Learning.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Assessing Robustness of Hyperdimensional Computing Against Errors in Associative Memory : (Invited Paper).
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
2020
Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators.
IEEE Des. Test, 2020
Model-Switching: Dealing with Fluctuating Workloads in Machine-Learning-as-a-Service Systems.
Proceedings of the 12th USENIX Workshop on Hot Topics in Cloud Computing, 2020
2019
CompAct: On-chip <underline>Com</underline>pression of <underline>Act</underline>ivations for Low Power Systolic Array Based CNN Acceleration.
ACM Trans. Embed. Comput. Syst., 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
IEEE Des. Test, 2019
Building Robust Machine Learning Systems: Current Progress, Research Challenges, and Opportunities.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators.
CoRR, 2018
Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
FATE: fast and accurate timing error prediction framework for low power DNN accelerator design.
Proceedings of the International Conference on Computer-Aided Design, 2018
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Int. J. Pattern Recognit. Artif. Intell., 2015