Avijit Dutta

Orcid: 0000-0003-2672-7331

Affiliations:
  • Institute for Advancing Intelligence, TCG-CREST, Kolkata, India


According to our database1, Avijit Dutta authored at least 53 papers between 2005 and 2024.

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Bibliography

2024
BBB security for 5-round even-Mansour-based key-alternating Feistel ciphers.
Des. Codes Cryptogr., January, 2024

2023
Tight Multi-User Security Bound of DbHtS.
IACR Trans. Symmetric Cryptol., 2023

On the Security of Triplex- and Multiplex-type Constructions with Smaller Tweaks.
IACR Cryptol. ePrint Arch., 2023

Tight Security Bound of 2k-LightMAC Plus.
IACR Cryptol. ePrint Arch., 2023

Cascading Four Round LRW1 is Beyond Birthday Bound Secure.
IACR Cryptol. ePrint Arch., 2023

sfPAE: Towards More Efficient and BBB-secure AE From a Single Public Permutation.
IACR Cryptol. ePrint Arch., 2023

Designing tweakable enciphering schemes using public permutations.
Adv. Math. Commun., 2023

Tight Security Bound of $\textsf {2k{\text {-}}LightMAC\_Plus}$.
Proceedings of the Progress in Cryptology - INDOCRYPT 2023, 2023

PAE: Towards More Efficient and BBB-Secure AE from a Single Public Permutation.
Proceedings of the Information and Communications Security - 25th International Conference, 2023

Proof of Mirror Theory for a Wide Range of $\xi _{\max }$.
Proceedings of the Advances in Cryptology - EUROCRYPT 2023, 2023

2022
Proof of Mirror Theory for ξ<sub>max</sub> = 2.
IEEE Trans. Inf. Theory, 2022

Tight Security Analysis of the Public Permutation-Based PMAC_Plus.
IACR Cryptol. ePrint Arch., 2022

Forking Sums of Permutations for Optimally Secure and Highly Efficient PRFs.
IACR Cryptol. ePrint Arch., 2022

Tight Multi-User Security Bound of sfDbHtS.
IACR Cryptol. ePrint Arch., 2022

INT-RUP Security of SAEB and TinyJAMBU.
IACR Cryptol. ePrint Arch., 2022

Proof of Mirror Theory for any $\xi_{\max}$.
IACR Cryptol. ePrint Arch., 2022

CENCPP<sup>*</sup>: beyond-birthday-secure encryption from public permutations.
Des. Codes Cryptogr., 2022

Multi-user BBB security of public permutations based MAC.
Cryptogr. Commun., 2022

2021
Improved Security Bound of (E/D)WCDM.
IACR Trans. Symmetric Cryptol., 2021

Permutation Based EDM: An Inverse Free BBB Secure PRF.
IACR Cryptol. ePrint Arch., 2021

Improved Security Bound of \textsf{(E/D)WCDM}.
IACR Cryptol. ePrint Arch., 2021

2020
Proof of Mirror Theory for $\xi_{\max}=2$.
IACR Cryptol. ePrint Arch., 2020

BBB Secure Nonce Based MAC Using Public Permutations.
IACR Cryptol. ePrint Arch., 2020

Minimizing the Two-Round Tweakable Even-Mansour Cipher.
IACR Cryptol. ePrint Arch., 2020

CENCPP - Beyond-birthday-secure Encryption from Public Permutations.
IACR Cryptol. ePrint Arch., 2020

Secure Proof of Ownership Using Merkle Tree for Deduplicated Storage.
Autom. Control. Comput. Sci., 2020

2019
Beyond Birthday Bound Secure MAC in Faulty Nonce Model.
IACR Cryptol. ePrint Arch., 2019

Tweakable HCTR: A BBB Secure Tweakable Enciphering Scheme.
IACR Cryptol. ePrint Arch., 2019

Release of Unverified Plaintext: Tight Unified Model and Application to ANYDAE.
IACR Cryptol. ePrint Arch., 2019

sfDWCDM+: A BBB secure nonce based MAC.
Adv. Math. Commun., 2019

2018
Encrypt or Decrypt? To Make a Single-Key Beyond Birthday Secure Nonce-Based MAC.
IACR Cryptol. ePrint Arch., 2018

Double-block Hash-then-Sum: A Paradigm for Constructing BBB Secure PRF.
IACR Cryptol. ePrint Arch., 2018

2017
A New Look at Counters: Don't Run Like Marathon in a Hundred Meter Race.
IEEE Trans. Computers, 2017

Tight Security Analysis of EHtM MAC.
IACR Cryptol. ePrint Arch., 2017

Single Key Variant of PMAC_Plus.
IACR Cryptol. ePrint Arch., 2017

The Iterated Random Function Problem.
IACR Cryptol. ePrint Arch., 2017

2016
Exact Security Analysis of Hash-then-Mask Type Probabilistic MAC Constructions.
IACR Cryptol. ePrint Arch., 2016

One-Key Compression Function Based MAC with Security Beyond Birthday Bound.
Proceedings of the Information Security and Privacy - 21st Australasian Conference, 2016

2015
Lifting the Security of NI-MAC Beyond Birthday Bound.
IACR Cryptol. ePrint Arch., 2015

2014
Deterministic Hard Fault Attack on Trivium.
Proceedings of the Advances in Information and Computer Security, 2014

2013
Canonical ordering of instances to immunize the FPGA place and route flow from ECO-induced variance.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memory.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

2011
A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores.
Proceedings of the 2011 IEEE International Test Conference, 2011

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.
Proceedings of the 2011 IEEE International Test Conference, 2011

2008
Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
Iterative OPDD Based Signal Probability Calculation.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Using Limited Dependence Sequential Expansion for Decompressing Test Vectors.
Proceedings of the 2006 IEEE International Test Conference, 2006

Partial Functional Manipulation Based Wirelength Minimization.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Synthesis of Efficient Linear Test Pattern Generators.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Synthesis of nonintrusive concurrent error detection using an even error detecting function.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005


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