Ayush Arunachalam

Orcid: 0000-0002-0750-0484

According to our database1, Ayush Arunachalam authored at least 8 papers between 2021 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Unlocking Hardware Security Assurance: The Potential of LLMs.
CoRR, 2023

Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits.
Proceedings of the IEEE International Test Conference, 2023

Search Space Reduction for Efficient Quantum Compilation.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Machine Learning-enhanced Efficient Spectroscopic Ellipsometry Modeling.
CoRR, 2022

Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs.
Proceedings of the IEEE International Test Conference, 2022

Fault Resilience of DNN Accelerators for Compressed Sensor Inputs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021
HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021


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