Amisha Srivastava

According to our database, Amisha Srivastava authored at least 14 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

PoSyn: Secure Power Side-Channel Aware Synthesis.

Amisha Srivastava, Samit Shahnawaz Miftah, Hyunmin Kim, Debjit Pal, Kanad Basu

IEEE Trans. Very Large Scale Integr. Syst., April, 2026

CryptRISC: A Secure RISC-V Processor for High-Performance Cryptography with Power Side-Channel Protection.

Amisha Srivastava, Muskan Porwal, Kanad Basu

CoRR, February, 2026

Microelectronics Systems Education - CHASE: A Cloud-Native Platform for Hardware Security.

Rahul Magesh, Amisha Srivastava, Sharath Pendyala, Samit Shahnawaz Miftah, Aydin Aysu, Kanad Basu

Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

2025

Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset.

Anand Menon, Samit Shahnawaz Miftah, Shamik Kundu, Souvik Kundu, Amisha Srivastava, Arnab Raha, Gabriel Theodor Sonnenschein, Suvadeep Banerjee, Deepak Mathaikutty, Kanad Basu

CoRR, March, 2025

OpenAssert: Towards Secure Assertion Generation using Large Language Models.

Anand Menon, Samit Shahnawaz Miftah, Amisha Srivastava, Shamik Kundu, Shovik Kundu, Arnab Raha, Suvadeep Banerjee, Deepak Mathaikutty, Kanad Basu

Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

SymbFuzz: Symbolic Execution Guided Hardware Fuzzing.

Samit Shahnawaz Miftah, Amisha Srivastava, Hyunmin Kim, Shiyi Wei, Kanad Basu

Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

2024

SCAR: Power Side-Channel Analysis at RTL Level.

Amisha Srivastava, Sanjay Das, Navnil Choudhury, Rafail Psiakis, Pedro Henrique Silva, Debjit Pal, Kanad Basu

IEEE Trans. Very Large Scale Integr. Syst., June, 2024

Hardware-based Detection of Malicious Firmware Modification in Microgrids.

Amisha Srivastava, Sneha Thakur, Abraham Peedikayil Kuruvila, Poras T. Balsara, Kanad Basu

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Yoga Pose Detection with Deep Learning and Computer Vision.

Amisha Srivastava, K. Gayathri, Senthil Kumar Thangavel, Pullela Meghana, S. Vishvajit, B. Senthil Kumar, K. Somasundaram

Proceedings of the 15th International Conference on Computing Communication and Networking Technologies, 2024

Assert-O: Context-based Assertion Optimization using LLMs.

Samit Shahnawaz Miftah, Amisha Srivastava, Hyunmin Kim, Kanad Basu

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance.

Xingyu Meng, Amisha Srivastava, Ayush Arunachalam, Avik Ray, Pedro Henrique Silva, Rafail Psiakis, Yiorgos Makris, Kanad Basu

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Unlocking Hardware Security Assurance: The Potential of LLMs.

Xingyu Meng, Amisha Srivastava, Ayush Arunachalam, Avik Ray, Pedro Henrique Silva, Rafail Psiakis, Yiorgos Makris, Kanad Basu

CoRR, 2023

Application Profiling Using Register-Instruction Hardware Performance Counters.

Anand Menon, Amisha Srivastava, Shamik Kundu, Kanad Basu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Search Space Reduction for Efficient Quantum Compilation.

Amisha Srivastava, Chao Lu, Navnil Choudhury, Ayush Arunachalam, Kanad Basu

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023