Balaji Vaidyanathan

According to our database1, Balaji Vaidyanathan authored at least 8 papers between 2006 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
NBTI-aware statistical circuit delay assessment.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2007
Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Architecting Microprocessor Components in 3D Design Space.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Process Scheduler-Based Approach to NoC Power Management.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Leakage Optimized DECAP Design for FPGAs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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