Ben Mathew

According to our database1, Ben Mathew authored at least 12 papers between 1992 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2007
Accurately Determining Bridging Defects from Layout.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2005
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2004
Understanding Yield Losses in Logic Circuits.
IEEE Des. Test Comput., 2004

Yield Analysis of Logic Circuits.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

1999
Combining multiple DFT schemes with test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
Testability Features of R10000 Microprocessor.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1995
DFT & ATPG: Together Again.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
Partial Reset: An Alternative DFT Approach.
VLSI Design, 1994

1993
On Selecting Flip-Flops for Partial Reset.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Augmented partial reset.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Robust switch-level test generation.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992


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