Vincenzo Tancorre
Orcid: 0000-0001-7959-0784
According to our database1,
Vincenzo Tancorre
authored at least 25 papers
between 2002 and 2023.
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Bibliography
2023
IEEE Trans. Computers, May, 2023
A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips.
IEEE Access, 2023
A guided debugger-based fault injection methodology for assessing functional test programs.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
On the integration and hardening of Software Test Libraries in Real-Time Operating Systems.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
About the Correlation between Logical Identified Faulty Gates and their Layout Characteristics.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
2022
IEEE Access, 2022
A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the 31st IEEE International Symposium on Industrial Electronics, 2022
An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip.
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the IEEE European Test Symposium, 2022
Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
2004
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
J. Electron. Test., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
2002
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002