Davide Appello
Orcid: 0000-0001-8178-2785
According to our database1,
Davide Appello
authored at least 54 papers
between 2001 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2023
IEEE Trans. Computers, May, 2023
A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips.
IEEE Access, 2023
A guided debugger-based fault injection methodology for assessing functional test programs.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
On the integration and hardening of Software Test Libraries in Real-Time Operating Systems.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
About the Correlation between Logical Identified Faulty Gates and their Layout Characteristics.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
2022
IEEE Access, 2022
A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the 31st IEEE International Symposium on Industrial Electronics, 2022
An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip.
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the IEEE European Test Symposium, 2022
Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
2020
Applicative System Level Test introduction to Increase Confidence on Screening Quality.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
2018
J. Low Power Electron., 2018
J. Electron. Test., 2018
2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
A mathematical model to assess the influence of parallelism in a semiconductor back-end test floor.
Proceedings of the International Test Conference in Asia, 2017
A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?
Proceedings of the 18th IEEE European Test Symposium, 2013
2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 14th IEEE European Test Symposium, 2009
2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 13th European Test Symposium, 2008
2007
Proceedings of the 2007 IEEE International Test Conference, 2007
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
2004
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
J. Electron. Test., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
A practical evaluation of I<sub>DDQ</sub> test strategies for deep submicron production test application. Experiences and targets from the field.
Proceedings of the 8th European Test Workshop, 2003
2002
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001