Bob Orr

According to our database1, Bob Orr authored at least 9 papers between 2014 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Wafer-level adaptive trim seed forecasting based on E-tests.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Harnessing process variations for optimizing wafer-level probe-test flow.
Proceedings of the 2016 IEEE International Test Conference, 2016

Harnessing fabrication process signature for predicting yield across designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A machine learning approach to fab-of-origin attestation.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
Yield prognosis for fab-to-fab product migration.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
IC laser trimming speed-up through wafer-level spatial correlation modeling.
Proceedings of the 2014 International Test Conference, 2014


  Loading...