John M. Carulli Jr.

According to our database1, John M. Carulli Jr. authored at least 38 papers between 2004 and 2024.

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Bibliography

2024
Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond.
IEEE Des. Test, 2024

2017
Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Systematic defect detection methodology for volume diagnosis: A data mining perspective.
Proceedings of the IEEE International Test Conference, 2017

2016
Controlling Aging in Timing-Critical Paths.
IEEE Des. Test, 2016

Consistency in wafer based outlier screening.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Pylon: Towards an integrated customizable volume diagnosis infrastructure.
Proceedings of the 2016 IEEE International Test Conference, 2016

Variation and failure characterization through pattern classification of test data from multiple test stages.
Proceedings of the 2016 IEEE International Test Conference, 2016

2015
Recycled IC Detection Based on Statistical Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Low-Cost Analog/RF IC Testing Through Combined Intra- and Inter-Die Correlation Models.
IEEE Des. Test, 2015

Yield prognosis for fab-to-fab product migration.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain.
Proc. IEEE, 2014

Reliability improvement of logic and clock paths in power-efficient designs.
ACM J. Emerg. Technol. Comput. Syst., 2014

Special session 11B: ITRS adaptive test update.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Innovative practices session 5C: Machine learning and data analysis in test.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling.
Proceedings of the 2014 International Test Conference, 2014

IC laser trimming speed-up through wafer-level spatial correlation modeling.
Proceedings of the 2014 International Test Conference, 2014

Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation.
Proceedings of the 2014 International Test Conference, 2014

Asymmetric aging of clock networks in power efficient designs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
Predicting die-level process variations from wafer test data for analog devices: A feasibility study.
Proceedings of the 14th Latin American Test Workshop, 2013

Process monitoring through wafer-level spatial variation decomposition.
Proceedings of the 2013 IEEE International Test Conference, 2013

Counterfeit electronics: A rising threat in the semiconductor manufacturing industry.
Proceedings of the 2013 IEEE International Test Conference, 2013

Test data analytics - Exploring spatial and test-item correlations in production test data.
Proceedings of the 2013 IEEE International Test Conference, 2013

A design-for-reliability approach based on grading library cells for aging effects.
Proceedings of the 2013 IEEE International Test Conference, 2013

Performance entitlement by exploiting transistor's BTI recovery.
Proceedings of the International Symposium on Quality Electronic Design, 2013

On combining alternate test with spatial correlation modeling in analog/RF ICs.
Proceedings of the 18th IEEE European Test Symposium, 2013

Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Spatial estimation of wafer measurement parameters using Gaussian process models.
Proceedings of the 2012 IEEE International Test Conference, 2012

Spatial correlation modeling for probe test cost reduction in RF devices.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Parametric counterfeit IC detection via Support Vector Machines.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Die-level adaptive test: Real-time test reordering and elimination.
Proceedings of the 2011 IEEE International Test Conference, 2011

2010
Adapting to adaptive testing.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Multidimensional Test Escape Rate Modeling.
IEEE Des. Test Comput., 2009

Quality improvement and cost reduction using statistical outlier methods.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
Modeling Test Escape Rate as a Function of Multiple Coverages.
Proceedings of the 2008 IEEE International Test Conference, 2008

2006
The Impact of Multiple Failure Modes on Estimating Product Field Reliability.
IEEE Des. Test Comput., 2006

2005
Test connections - tying application to process.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Impact of Negative Bias Temperature Instability on Product Parametric Drift.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004


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