Byungki Han
According to our database1,
Byungki Han
authored at least 7 papers
between 2014 and 2024.
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Bibliography
2024
4.3 A 43mm<sup>2</sup> Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 4×4 MIMO with 1K-QAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2020
A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2017
A 14nm FinFET analog baseband SOC for multi-mode cellular applications with tri-band carrier aggregation.
Proceedings of the International SoC Design Conference, 2017
A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2014
A reconfigurable analog baseband for single-chip, Saw-less, 2G/3G/4G cellular transceivers with carrier aggregation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014