Cenlin Duan

According to our database, Cenlin Duan authored at least 11 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

ACE-GNN: Adaptive GNN Co-Inference With System-Aware Scheduling in Dynamic Edge Environments.

Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Xinming Wei, Cenlin Duan, Weisheng Zhao, Chunming Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2026

Efficient SRAM-PIM Co-Design by Joint Exploration of Value-Level and Bit-Level Sparsity.

Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2026

CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-Based CIM Architectures.

Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao

IEEE Trans. Computers, January, 2026

MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator.

Xiaolin He, Cenlin Duan, Yingjie Qi, Xiao May, Jianlei Yang

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator.

Xiaolin He, Cenlin Duan, Yingjie Qi, Xiao Ma, Jianlei Yang

CoRR, October, 2025

HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference.

Cenlin Duan, Jianlei Yang, Rubing Yang, Yikun Wang, Yiou Wang, Lingkun Long, Yingjie Qi, Xiaolin He, Ao Zhou, Xueyan Wang, Weisheng Zhao

CoRR, September, 2025

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures.

Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices.

Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu

IEEE Trans. Computers, December, 2024

DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.

Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity.

Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2022

Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM.

Zhengyi Hou, Zhaohao Wang, Chao Wang, Min Wang, You Wang, Xueyan Wang, Cenlin Duan, Jianlei Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022