Weitao Pan

According to our database, Weitao Pan authored at least 29 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.

Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

2023

Access mechanism for period flows of non-deterministic end systems for time-sensitive networks.

Zhe Zhao, Lu Gao, Weitao Pan, Zhiliang Qiu, Xu Guo, Ya Gao, Ling Zheng

Comput. Networks, July, 2023

A unioned graph neural network based hardware Trojan node detection.

Weitao Pan, Meng Dong, Cong Wen, Hongjin Liu, Shaolin Zhang, Bo Shi, Zhixiong Di, Zhiliang Qiu, Yiming Gao, Ling Zheng

IEICE Electron. Express, 2023

A Machine Learning Based Approach to Detect Machine Learning Design Patterns.

Weitao Pan, Hironori Washizaki, Nobukazu Yoshioka, Yoshiaki Fukazawa, Foutse Khomh, Yann-Gaël Guéhéneuc

Proceedings of the 30th Asia-Pacific Software Engineering Conference, 2023

2022

Evaluation Method for Feature Selection in Proton Exchange Membrane Fuel Cell Fault Diagnosis.

Lei Mao, Zhongyong Liu, Derek Low, Weitao Pan, Qingbo He, Lisa M. Jackson, Qiang Wu

IEEE Trans. Ind. Electron., 2022

A Universal, Low-Delay, SEC-DEC-TAEC Code for State Register Protection.

Meng Dong, Weitao Pan, Zhiliang Qiu, Xiaoxin Qi, Ling Zheng, Huan Liu

IEEE Access, 2022

Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform.

Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal.

Jiangyi Shi, Xinyuan Zhang, Peijun Ma, Weitao Pan, Pengfei Li, Zhengguang Tang

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Low-Cost and Programmable CRC Implementation Based on FPGA.

Huan Liu, Zhiliang Qiu, Weitao Pan, Jun Li, Ling Zheng, Ya Gao

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Architecture design and performance analysis of a novel memory system for high-bandwidth onboard switching fabric.

Ling Zheng, Weitao Pan, Ya Gao, Huan Liu, Jing Jiang

Comput. Networks, 2021

GGTS: FPGA-Based General Ground Test System for Space-Borne Equipment.

Jialu Mang, Zhiliang Qiu, Weitao Pan, Meng Dong, Min Wu

Proceedings of the 6th IEEE International Conference on Computer and Communication Systems, 2021

Design of HIMAC Coprocessor for HINOC3.0.

Jinjian Huang, Zhiliang Qiu, Weitao Pan, Jun Li, Zhikai Gao, Bing Han, Zihao Xiong, Meng Dong

Proceedings of the 6th IEEE International Conference on Computer and Communication Systems, 2021

Design and Implementation of AS6802 Clock Synchronization System in TTE thernet.

Jinlong Dong, Zhiliang Qiu, Weitao Pan, Min Wu, Jialiang Cao

Proceedings of the 6th IEEE International Conference on Computer and Communication Systems, 2021

Combined Shared-Memory and Buffered-Crossbar Architecture for High-Bandwidth Onboard Switching Fabric.

Ling Zheng, Chen Yi, Weitao Pan, Huan Liu

Proceedings of the APNet 2021: 5th Asia-Pacific Workshop on Networking, Shenzhen, China, June 24, 2021

HyperParser: A High-Performance Parser Architecture for Next Generation Programmable Switch and SmartNIC.

Huan Liu, Zhiliang Qiu, Weitao Pan, Jiajun Li, Jinjian Huang

Proceedings of the APNet 2021: 5th Asia-Pacific Workshop on Networking, Shenzhen, China, June 24, 2021

2020

Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high-performance shared-memory switches.

Ling Zheng, Weitao Pan, Yinghua Li, Ya Gao

Int. J. Commun. Syst., 2020

High-Performance and Range-Supported Packet Classification Algorithm for Network Security Systems in SDN.

Ling Zheng, Jing Jiang, Weitao Pan, Huan Liu

Proceedings of the 2020 IEEE International Conference on Communications Workshops, 2020

Dual-Plane Switch Architecture for Time-Triggered Ethernet.

Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin, Jianlei Yang

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

AFBV: A High-Performance Network Flow Classification Method for Multi-Dimensional Fields and FPGA Implementation.

Ling Zheng, Zhiliang Qiu, Weina Wang, Weitao Pan, Shiyong Sun, Ya Gao

J. Circuits Syst. Comput., 2019

2018

Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers.

Ling Zheng, Zhiliang Qiu, Shiyong Sun, Weitao Pan, Ya Gao, Zhiyi Zhang

J. Commun. Networks, 2018

Analysis and Implementation of a QoS Optimization Method for Access Networks.

Ling Zheng, Zhiliang Qiu, Weitao Pan, Yibo Mei, Shiyong Sun, Zhiyi Zhang

IEICE Trans. Commun., 2018

Analysis of a Shared-Private Buffer Management Scheme for Shared Memory Switches.

Ling Zheng, Zhiliang Qiu, Weitao Pan, Ya Gao, Junxiang Zhang, Dong Zhang

Proceedings of the 2018 International Conference on Computer, 2018

The High Speed Packet Classification Supporting Multi - Field for Flow Tables in OpenFlow.

Zhiliang Qiu, Weina Wang, Shiyong Sun, Weitao Pan, Ling Zheng, Ya Gao, Zhiyi Zhang

Proceedings of the 2018 International Conference on Computer, 2018

Research on Model of Five-level Scheduling Based on SDN.

Weitao Pan, Lili Gao, Ling Zheng, Zhiliang Qiu, Junxiang Zhang, Dong Zhang, Ya Gao

Proceedings of the 2018 International Conference on Computer, 2018

The Design and Implementation of IEEE 1588v2 Clock Synchronization System by Generating Hardware Timestamps in MAC Layer.

Meng Dong, Zhiliang Qiu, Weitao Pan, Can Chen, Junxiang Zhang, Dong Zhang

Proceedings of the 2018 International Conference on Computer, 2018

A High-Speed Large-Capacity Packet Buffer Scheme for High-Bandwidth Switches and Routers.

Ling Zheng, Zhiliang Qiu, Weitao Pan, Ya Gao

Proceedings of the Communications and Networking, 2018

2017

Improved analytical model for performance evaluation of crosspoint-queued switch under uniform traffic.

Ya Gao, Weitao Pan, Ling Zheng

IET Networks, 2017

Analyzing the Impact of Redundant Paths on Multistage Switch Performance.

Ya Gao, Weitao Pan, Ling Zheng

Proceedings of the Communications and Networking, 2017

2016

Dual priority congestion aware shared-resource Network-on-Chip architecture.

Hao Shu, Jiangyi Shi, Peijun Ma, Huaxi Gu, Weitao Pan, Lin-An Yang

IEICE Electron. Express, 2016