Chang-Tzu Lin

According to our database, Chang-Tzu Lin authored at least 21 papers between 2002 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Learning Based Placement Refinement to Reduce DRC Short Violations.

Ying-Yao Huang, Chang-Tzu Lin, Wei-Lun Liang, Hung-Ming Chen

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

2019

More Effective Power Network Prototyping by Analytical and Centroid Learning.

Yu-Hsiang Chuang, Chang-Tzu Lin, Hung-Ming Chen, Chi-Han Lee, Ting-Sheng Chen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017

On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC.

Sheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, Ding-Ming Kwai, Yung-Fa Chou

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization.

Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

A New Methodology for Noise Sensor Placement Based on Association Rule Mining.

Yu-Hsiang Hung, Sheng-Hsin Fang, Hung-Ming Chen, Shen-Min Chen, Chang-Tzu Lin, Chia-Hsin Lee

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2014

A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage.

Tsu-Wei Tseng, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Improving power delivery network design by practical methodologies.

Chia-Chi Huang, Chang-Tzu Lin, Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, Chia-Hsin Lee, Ding-Ming Kwai

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Enabling inter-die co-optimization in 3-D IC with TSVs.

Chang-Tzu Lin, Tsu-Wei Tseng, Yung-Fa Chou, Chia-Hsin Lee, Ding-Ming Kwai

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Effective power network prototyping via statistical-based clustering and sequential linear programming.

Shih-Ying Sean Liu, Chieh-Jui Lee, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee

Proceedings of the Design, Automation and Test in Europe, 2013

I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs.

Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

3-D centric technology and realization with TSV.

Chang-Tzu Lin, Chia-Hsin Lee, Tsu-Wei Tseng, Ding-Ming Kwai, Yung-Fa Chou

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Hierarchical power network synthesis for multiple power domain designs.

Chieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement.

Ding-Ming Kwai, Chang-Tzu Lin

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

CAD reference flow for 3D via-last integrated circuits.

Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2007

Fixed-outline floorplanning using robust evolutionary search.

De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang, Ching-Hwa Cheng

Eng. Appl. Artif. Intell., 2007

Noise-Aware Floorplanning for Fast Power Supply Network Design.

Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang, Ching-Hwa Cheng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm.

Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang

J. Circuits Syst. Comput., 2006

2005

Modem floorplanning with abutment and fixed-outline constraints.

Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang, Hsin-Hsien Ho

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Robust fixed-outline floorplanning through evolutionary search.

Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Non-slicing floorplans with boundary constraints using generalized polish expression.

De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

GPE: A New Representation for VLSI Floorplan Problem.

Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002