Wen Ching Wu

According to our database, Wen Ching Wu authored at least 16 papers between 1991 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories.

Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

Diagnosis of MRAM Write Disturbance Fault.

Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao

IEEE Trans. Very Large Scale Integr. Syst., 2010

CAD reference flow for 3D via-last integrated circuits.

Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2008

Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.

Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.

Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu

IEEE Trans. Very Large Scale Integr. Syst., 2007

Diagnosis for MRAM write disturbance fault.

Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle.

Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.

Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

MRAM Defect Analysis and Fault Modeli.

Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2000

Oscillation Ring Delay Test for High Performance Microprocessors.

Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir

J. Electron. Test., 2000

1998

A Two-Phase Fault Simulation Scheme for Sequential Circuits.

Wen Ching Wu, Chung-Len Lee, Jwu E. Chen

J. Inf. Sci. Eng., 1998

1997

Fault diagnosis of odd-even sorting networks.

Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1995

Identification of robust untestable path delay faults.

Wen Ching Wu, Chung-Len Lee, Jwu E. Chen

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning.

Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1991

A Probabilistic Testability Measure for Delay Faults.

Wen Ching Wu, Chung-Len Lee

Proceedings of the 28th Design Automation Conference, 1991