Changsik Shin

According to our database1, Changsik Shin authored at least 7 papers between 2008 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A 10.1" 183-µW/electrode, 0.73-mm2/sensor High-SNR 3-D Hover Sensor Based on Enhanced Signal Refining and Fine Error Calibrating Techniques.
IEEE J. Solid State Circuits, 2018

A 95.2% efficiency dual-path DC-DC step-up converter with continuous output current delivery and low voltage ripple.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016
A reconfigurable SIMO system with 10-output dual-bus DC-DC converter using the load balancing function in group allocator for diversified load condition.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
12.1 A 0.518mm<sup>2</sup> quasi-current-mode hysteretic buck DC-DC converter with 3μs load transient response in 0.35μm BCDMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2011
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks.
J. Circuits Syst. Comput., 2011

2009
ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008
Power-gating-aware high-level synthesis.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008


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