Min-Woo Ko

Orcid: 0000-0001-5901-6320

According to our database1, Min-Woo Ko authored at least 9 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A Bipolar-Output Switched-Capacitor DC-DC Boost Converter With Residual-Energy-Recycling Regulation and Low Dropout Post-Filtering Techniques.
IEEE J. Solid State Circuits, May, 2023

2022
A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
A 4.5V-Input 0.3-to-1.7V-Output Step-Down Always-Dual-Path DC-DC Converter Achieving 91.5%-Efficiency with 250mΩ-DCR Inductor for Low-Voltage SoCs.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

17.8 A 90.5%-Efficiency 28.7µ VRMS-Noise Bipolar-Output High-Step-Up SC DC-DC Converter with Energy-Recycled Regulation and Post-Filtering for ±15V TFT-Based LAE Sensors.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
An 8Ω, 1.4W, 0.0024% THD+N Class-D Audio Amplifier with Bridge-Tied Load Half-Side Switching Mode Achieving Low Standby Quiescent Current of 660μA.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

11.8 A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
A 95.2% efficiency dual-path DC-DC step-up converter with continuous output current delivery and low voltage ripple.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 97% high-efficiency 6μs fast-recovery-time buck-based step-up/down converter with embedded 1/2 and 3/2 charge-pumps for li-lon battery management.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 100mK-NETD 100ms-startup-time 80×60 micro-bolometer CMOS thermal imager integrated with a 0.234mm<sup>2</sup> 1.89μVrms noise 12b biasing DAC.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018


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