Charalampos Antoniadis
Orcid: 0000-0002-5902-5240
According to our database1,
Charalampos Antoniadis
authored at least 26 papers
between 2013 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Best Memory Architecture Exploration under Parameters Variations accelerated with Machine Learning.
CoRR, 2023
Enhancing DNN Models for EEG/ECoG BCI With a Novel Data-Driven Offline Optimization Method.
IEEE Access, 2023
Solar-Powered Vehicle-to-Load (V2L) Plug-in Electric Vehicles: Alleviation of the Photovoltaic Power Decay.
Proceedings of the IEEE International Conference on Smart Mobility, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Modified Bat Algorithm with Reduced Search Space Exploration for MPPT under Dynamic Partial Shading Conditions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
An ElectroStatic Discharge Algorithm for Electric Vehicle Li Ion Battery Parameters Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Low Power Hardware Architecture for Sampling-free Bayesian Neural Networks inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
IEEE Access, 2022
A Dense Explorative ElectroStatic Discharge optimization Algorithm for Photovoltaic Parameters Estimation.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Audio-visual Speaker Diarization: Improved Voice Activity Detection with CNN based Feature Extraction.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A Novel Approach to the Maximum Peak Power Tracking under Partial Shading conditions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Graph-Based Sparsification and Synthesis of Dense Matrices in the Reduction of RLC Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2021
2019
A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects.
Proceedings of the 16th International Conference on Synthesis, 2019
Efficient Linear System Solution Techniques in the Simulation of Large Dense Mutually Inductive Circuits.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
A Rigorous Approach for the Sparsification of Dense Matrices in Model Order Reduction of RLC Circuits.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Proceedings of the 15th International Conference on Synthesis, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
2013
Fast and accurate BER estimation methodology for I/O links based on extreme value theory.
Proceedings of the Design, Automation and Test in Europe, 2013