Nestoras E. Evmorfopoulos

Orcid: 0000-0002-6968-0222

According to our database1, Nestoras E. Evmorfopoulos authored at least 56 papers between 1999 and 2024.

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Bibliography

2024
MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits.
CoRR, 2024

2023
Fast electromigration stress analysis using Low-Rank Balanced Truncation for general interconnect and power grid structures.
Integr., March, 2023

Reduction of large-scale RLCk models via low-rank balanced truncation.
CoRR, 2023

Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential.
Proceedings of the 19th International Conference on Synthesis, 2023

PROTON - A Python Framework for Physics-Based Electromigration Assessment on Contemporary VLSI Power Grids.
Proceedings of the 19th International Conference on Synthesis, 2023

An Optimal Methodology for EM-Based Hardware Trojan Placement on Clock Tree Networks.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Frequency-Domain Transient Electromigration Analysis Using Circuit Theory.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

On the Reduction of Large-Scale Room Acoustic Models.
Proceedings of the IEEE International Conference on Acoustics, 2023

A System Theoretic Approach for the Reduction of Large-Scale Room Acoustic Models.
Proceedings of the 31st European Signal Processing Conference, 2023

An Efficient Security Closure Methodology for EM-based Attacks on Power Grid Structures.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees Using Matrix Exponential.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
The Extended and Asymmetric Extended Krylov Subspace in Moment-Matching-Based Order Reduction of Large Circuit Models.
CoRR, 2022

Accelerating Electromigration Stress Analysis Using Low-Rank Balanced Truncation.
Proceedings of the 18th International Conference on Synthesis, 2022

A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment Interconnects.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Graph-Based Sparsification and Synthesis of Dense Matrices in the Reduction of RLC Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Statistical Estimation of Leakage Power Bounds in CMOS VLSI Circuits.
Proceedings of the PCI 2021: 25th Pan-Hellenic Conference on Informatics, Volos, Greece, November 26, 2021

Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Frequency-Limited Reduction of Regular and Singular Circuit Models Via Extended Krylov Subspace Method.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2019
Efficient IC hotspot thermal analysis via low-rank Model Order Reduction.
Integr., 2019

A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects.
Proceedings of the 16th International Conference on Synthesis, 2019

Efficient Circuit Reduction in Limited Frequency Windows.
Proceedings of the 16th International Conference on Synthesis, 2019

Multiple Transient Faults in Combinational Logic with Placement Considerations.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Efficient Linear System Solution Techniques in the Simulation of Large Dense Mutually Inductive Circuits.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

A Rigorous Approach for the Sparsification of Dense Matrices in Model Order Reduction of RLC Circuits.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Efficient sparsification of dense circuit matrices in model order reduction.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPU s.
Proceedings of the 15th International Conference on Synthesis, 2018

Efficient Hotspot Thermal Simulation Via Low-Rank Model Order Reduction.
Proceedings of the 15th International Conference on Synthesis, 2018

On the Sparsification of the Reluctance Matrix in RLCk Circuit Transient Analysis.
Proceedings of the 15th International Conference on Synthesis, 2018

Large scale circuit simulation exploiting combinatorial multigrid on massively parallel architectures.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

A parallel iterative approach for efficient full chip thermal analysis.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

EVT-based worst case delay estimation under process variation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Placement-based SER estimation in the presence of multiple faults in combinational logic.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016
Parallel Fast Transform-Based Preconditioners for Large-Scale Power Grid Analysis on Graphics Processing Units (GPUs).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015
On the statistical memory architecture exploration and optimization.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
A 3-D Fast Transform-based preconditioner for large-scale power grid analysis on massively parallel architectures.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Selective Inversion of Inductance Matrix for Large-Scale Sparse RLC Simulation.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
A parallel fast transform-based preconditioning approach for electrical-thermal co-simulation of power delivery networks.
Proceedings of the Design, Automation and Test in Europe, 2013

Fast and accurate BER estimation methodology for I/O links based on extreme value theory.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Fast Transform-based preconditioners for large-scale power grid analysis on massively parallel architectures.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2010
A power grid analysis and verification tool based on a Statistical Prediction Engine.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2008
A Design Flow for the Precise Identification of the Worst-Case Voltage Drop in Power Grid Analyses.
Proceedings of the Panhellenic Conference on Informatics, 2008

A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions.
Proceedings of the 26th International Conference on Computer Design, 2008

2006
Precise identification of the worst-case voltage drop conditions in power grid verification.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2004
Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimates.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2002
A Monte Carlo approach for maximum power estimation based onextreme value theory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

1999
Adaptive digital fuzzy hardware in application-specific integrated circuits.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999


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