Alessandro Cevrero
According to our database1,
Alessandro Cevrero
authored at least 46 papers
between 2008 and 2020.
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Bibliography
2020
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.
IEEE J. Solid State Circuits, 2020
2019
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018
A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018
A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels.
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE J. Solid State Circuits, 2017
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Adaptive high-speed and ultra-low power optical interconnect for data center communications.
Proceedings of the 2017 19th International Conference on Transparent Optical Networks (ICTON), 2017
Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
Microelectron. J., 2016
Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors.
Microelectron. J., 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Fast and accurate BER estimation methodology for I/O links based on extreme value theory.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
2011
Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library.
Proceedings of the 48th Design Automation Conference, 2011
2010
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
2009
ACM Trans. Reconfigurable Technol. Syst., 2009
Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation.
Proceedings of the FCCM 2009, 2009
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009
2008
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008
Proceedings of the 2008 International Conference on Compilers, 2008