Vasilis F. Pavlidis

Orcid: 0000-0002-4063-4652

According to our database1, Vasilis F. Pavlidis authored at least 81 papers between 2001 and 2024.

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Bibliography

2024
MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits.
CoRR, 2024

A New Dataflow Implementation to Improve Energy Efficiency of Monolithic 3D Systolic Arrays.
CoRR, 2024

Enhanced Detection of Thermal Covert Channel Attacks in Multicore Processors.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Mismatch Driven Systematic Design Methodology for Transistor Based Active Resistors.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Novel Design Methodology for Modular, Digitally Controlled, Multiband, mmWave LNAs.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

2022
Energy-Efficient Encoding for High-Speed Serial Interfaces.
IEEE Trans. Very Large Scale Integr. Syst., 2022

High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective.
Integr., 2022

Temperature-Aware Monolithic 3D DNN Accelerators for Biomedical Applications.
CoRR, 2022

Practical Day-Ahead Power Prediction of Solar Energy-Harvesting for IoT Systems.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Thermal Modeling and Design Exploration for Monolithic 3D ICs.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Mitigating EM Side-Channel Attacks with Dynamic Delay Insertion and Data Bus Inversion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Design of compact LC lowpass filters based on coaxial through-silicon vias array.
Microelectron. J., 2021

TSV-based hairpin bandpass filter for 6G mobile communication applications.
IEICE Electron. Express, 2021

Performance-Aware Interconnect Delay Insertion Against EM Side-Channel Attacks.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

A PWM-free DC-DC Boost Converter with 0.43 V Input for Extended Battery Use in IoT Applications.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Energy-Efficient Time-Based Adaptive Encoding for Off-Chip Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Metal Stack and Partitioning Exploration for Monolithic 3D ICs.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Cost Modeling and Analysis of TSV and Contactless 3D-ICs.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Fabrication Cost Analysis for Contactless 3-D ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Efficient Linear System Solution Techniques in the Simulation of Large Dense Mutually Inductive Circuits.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICs.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Adaptive Transient Leakage-Aware Linearised Model for Thermal Analysis of 3-D ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Adaptive Word Reordering for Low-Power Inter-Chip Communication.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Efficient Modeling of Crosstalk Noise on Power Distribution Networks for Contactless 3-D ICs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

The MTA: An Advanced and Versatile Thermal Simulator for Integrated Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Contactless Heterogeneous 3-D ICs for Smart Sensing Systems.
Integr., 2018

Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Ultra-low swing CMOS transceiver for 2.5-D integrated systems.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Mismatch Compensation Technique for Inverter-Based CMOS Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Voltage scaling for 3-D ICs: When, how, and how much?
Microelectron. J., 2017

STA compatible backend design flow for TSV-based 3-D ICs.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Contactless inter-tier communication for heterogeneous 3-D ICs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Computationally efficient standard-cell FEM-based thermal analysis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Application performance improvement by exploiting process variability on FPGA devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Crosstalk noise effects of on-chip inductive links on power delivery networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled Interconnects.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Interconnect design tradeoffs for silicon and glass interposers.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Efficient teaching of digital design with automated assessment and feedback.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

2013
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise.
IEEE Trans. Very Large Scale Integr. Syst., 2013

An Enhanced Design Methodology for Resonant Clock Trees.
J. Low Power Electron., 2013

3.5-D integration: A case study.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric.
ACM Trans. Reconfigurable Technol. Syst., 2012

Inter-Plane Communication Methods for 3-D ICs.
J. Low Power Electron., 2012

Effect of process variations in 3D global clock distribution networks.
ACM J. Emerg. Technol. Comput. Syst., 2012

The combined effect of process variations and power supply noise on clock skew and jitter.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Enhanced wafer matching heuristics for 3-D ICs.
Proceedings of the 17th IEEE European Test Symposium, 2012

Voltage propagation method for 3-D power grid analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Physical Analysis of NoC Topologies for 3-D Integrated Systems.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Clock Distribution Networks in 3-D Integrated Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Skew variability in 3-D ICs with multiple clock domains.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Clock distribution models of 3-D integrated systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Analytical heat transfer model for thermal through-silicon vias.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Process-induced skew variation for scaled 2-D and 3-D ICs.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Physical design tradeoffs in power distribution networks for 3-D ICs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Synchronization and power integrity issues in 3-D ICs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Performance analysis of 3-D monolithic integrated circuits.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits.
Proc. IEEE, 2009

Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

Power distribution paths in 3-D ICS.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Timing-driven via placement heuristics for three-dimensional ICs.
Integr., 2008

Physical Design Issues in 3-D Integrated Technologies.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

Clock distribution networks for 3-D ictegrated Circuits.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
3-D Topologies for Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A software-supported methodology for designing high-performance 3D FPGA architectures.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support.
Proceedings of the FPL 2007, 2007

2006
Via placement for minimum interconnect delay in three-dimensional (3D) circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Interconnect delay minimization through interlayer via placement in 3-D ICs.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2003
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
Designing low-power energy recovery adders based on pass transistor logic.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001


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