Tin Tin Wee

According to our database1, Tin Tin Wee authored at least 6 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019

2012
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors.
IEEE J. Solid State Circuits, 2012

2011
Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2009
Loopback architecture for wafer-level at-speed testing of embedded HyperTransport<sup>TM</sup> processor links.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2006
A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking.
IEEE J. Solid State Circuits, 2006

2005


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