Chin-Hung Wang

Orcid: 0009-0005-3613-083X

According to our database1, Chin-Hung Wang authored at least 7 papers between 2009 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Corrections to "Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach".
IEEE Trans. Very Large Scale Integr. Syst., October, 2025

Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach.
IEEE Trans. Very Large Scale Integr. Syst., September, 2025

Miniaturized and Cost-Effective Programmable 2.5D/3.5D Platforms Enabled by Scalable Embedded Active Bridge Chipset.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2025

2024
Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022
An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2009
A DEP chip with arc-shape microelectrode arrays for the separation of different-size particles.
Proceedings of the 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2009

An improvement of secure authentication scheme with full anonymity for wireless communications.
Proceedings of the 2nd International Conference on Interaction Sciences: Information Technology, 2009


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