Chris J. Nicol

Orcid: 0009-0009-1681-3907

According to our database1, Chris J. Nicol authored at least 23 papers between 1993 and 2025.

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Bibliography

2025
Corsair: An In-Memory Computing Chiplet Architecture for Inference-Time Compute Acceleration.
IEEE Micro, 2025

2015
Session 24 overview: Secure, efficient circuits for IoT: Technology directions subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2006
A Scalable 7.2 Mb/s 3GPP HSDPA Co-processor with Advanced NLMS Receiver and Receive Diversity for Mobile Terminals.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A 28.8 Mb/s 4 × 4 MIMO 3G CDMA receiver for frequency selective channels.
IEEE J. Solid State Circuits, 2005

2004
An eight-user UMTS channel unit Processor for 3GPP base station applications.
IEEE J. Solid State Circuits, 2004

2003
Integrated circuits for channel coding in 3G cellular mobile wireless systems.
IEEE Commun. Mag., 2003

Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003


2002
A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2002

A low power normalized-LMS decision feedback equalizer for a wireless packet modem.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Integrated circuits for 3GPP mobile wireless systems.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
Energy efficient turbo decoding for 3G mobile.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Low power DSP's for wireless communications (embedded tutorial session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

DSP systems for next-generation mobile wireless infrastructure.
Proceedings of the IEEE International Conference on Acoustics, 2000

1999
A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
High performance DSPs - what's hot and what's not?
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Reconfigurable hardware for efficient implementation of programmable FIR filters.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997
A low-power 128-tap digital adaptive equalizer for broadband modems.
IEEE J. Solid State Circuits, 1997

Low power multiplication for FIR filters.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996
A scalable pipelined architecture for fast buffer SRAMs.
IEEE J. Solid State Circuits, 1996

Transition reduction in carry-save adder trees.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1994
Application Specific Memories for ATM Packet Switching.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
A Systolic Architecture for High Speed Pipelined Memories.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


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