Chu Yu

Orcid: 0000-0003-2813-9605

According to our database¹, Chu Yu authored at least 40 papers between 1999 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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Links

On csauthors.net:

Bibliography

2024

Generic Hardware Integrating Multiple Activation Functions for Deep Learning Applications.

[BibT_eX]

[DOI]

Chu Yu

Yi-Ching Hung

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

2023

Efficient Max Pooling Architecture with Zero-Padding for Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2022

Realization of a Real-Time Image Denoising System for Dashboard Camera Applications.

[BibT_eX]

[DOI]

Chu Yu

Li-Zhong Hou

IEEE Trans. Consumer Electron., 2022

2020

Friendly Appearance of Multiple Secret Sharing.

[BibT_eX]

[DOI]

Heri Prasetyo

Chih-Hsien Hsia

Chu Yu

Albertus Ricky Wirawan

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019

Peer Group and Hybrid Vector Filter for Removal of Impulse Noise in Color Images.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

2018

Three-Parallel Reed-Solomon Decoder using a Simplified Step-by-Step Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th Global Conference on Consumer Electronics, 2018

2017

Low-complexity twiddle factor generator for FFT processors.

[BibT_eX]

[DOI]

Chu Yu

Kuang-Hsiao Lee

Chien-Feng Kuo

Proceedings of the IEEE International Conference on Consumer Electronics, 2017

Lower bit-error-rate polar-LDPC concatenated coding for wireless communication systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

2015

Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems.

[BibT_eX]

[DOI]

Chu Yu

Mao-Hsu Yen

IEEE Trans. Very Large Scale Integr. Syst., 2015

Two-Mode Reed-Solomon Decoder Using A Simplified Step-by-Step Algorithm.

[BibT_eX]

[DOI]

Chu Yu

Yu-Shan Su

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Comment on "On Optimal Hyperuniversal and Rearrangeable Switch Box Designs".

[BibT_eX]

[DOI]

Mao-Hsu Yen

Hung-Kuan Yen

Chu Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Variable code length soft-output decoder of polar codes.

[BibT_eX]

[DOI]

Jung-Hong Po

Sao-Jie Chen

Chu Yu

Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

An effective spatial-temporal denoising approach for depth images.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Efficient image denoising scheme for removal of impulse noise.

[BibT_eX]

[DOI]

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

2014

Incorporation of perceptually adaptive QIM with singular value decomposition for blind audio watermarking.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2014

Improvement on a block-serial fully-overlapped QC-LDPC decoder for IEEE 802.11n.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2014

2013

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design.

[BibT_eX]

[DOI]

VLSI Design, 2013

Design of a (255, 239) Reed-Solomon decoder using a simplified step-by-step algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Consumer Electronics, 2013

A dual-code-rate memoryless Viterbi decoder for wireless communication systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2013

A 128/512/1024/2048-point pipeline FFT/IFFT architecture for mobile WiMAX.

[BibT_eX]

[DOI]

Chu Yu

Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

Hyper-Universal Switch Network for FPIC Design.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on Complex, 2013

2012

Design and implementation of a low-power OFDM receiver for wireless communications.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2012

A HMM-WDLT framework for HNM-based voice conversion with parametric adjustment in formant bandwidth, duration and excitation.

[BibT_eX]

[DOI]

Hwai-Tsu Hu

Chu Yu

Int. J. Speech Technol., 2012

A Perceptually Adaptive QIM Scheme for Efficient Watermark Synchronization.

[BibT_eX]

[DOI]

Hwai-Tsu Hu

Chu Yu

IEICE Trans. Inf. Syst., 2012

Design of a low-power OFDM baseband receiver for wireless communications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2012

A Ubiquitous Scheme for a One-to-Many Switching Tunnel for Healthcare Utilization.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Conference on Computational Intelligence, 2012

2011

A low-power 64-point pipeline FFT/IFFT processor for OFDM applications.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2011

2010

Low power design of phase-change memory based on a comprehensive model.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2010

ARAL-CR: An adaptive reasoning and learning cognitive radio platform.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Perfect shuffling for cycle efficient puncturer and interleaver for software defined radio.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Combining HMM and Weighted Deviation Linear Transformation for Highband Speech Parameter Estimation.

[BibT_eX]

[DOI]

Hwai-Tsu Hu

Chu Yu

IEICE Trans. Inf. Syst., 2009

An instruction set architecture independent design method for embedded OFDM-based software defined transmitter.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Parallel implementation of convolution encoder for software defined radio on DSP architecture.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

A 900 MHz to 5.2 GHz Dual-loop Feedback Multi-band LNA.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007

A compact pipelined architecture with high-throughput for context-based binary arithmetic coding.

[BibT_eX]

[DOI]

Chu Yu

Hwai-Tsu Hu

Proceedings of the 2007 IEEE International SOC Conference, 2007

2003

Design and implantation of an ASIC architecture for 1.6 kbps speech synthesis.

[BibT_eX]

[DOI]

Chu Yu

Hwai-Tsu Hu

Chen-Yen Lin

IEEE Trans. Consumer Electron., 2003

An efficient architecture for 2-D biorthogonal inverse discrete wavelet transforms.

[BibT_eX]

[DOI]

Chu Yu

IEEE Trans. Consumer Electron., 2003

Determination of glottal closure instants by harmonic superposition.

[BibT_eX]

[DOI]

Hwai-Tsu Hu

Shun-Ta Hsu

Chu Yu

Signal Process., 2003

1999

Design of an efficient VLSI architecture for 2-D discrete wavelet transforms.

[BibT_eX]

[DOI]

Chu Yu

Sao-Jie Chen

IEEE Trans. Consumer Electron., 1999

Efficient VLSI architecture for 2-D inverse discrete wavelet transforms.

[BibT_eX]

[DOI]

Chu Yu

Sao-Jie Chen

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Chu Yu

Timeline

Legend:

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On csauthors.net:

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