Ming-Jer Kao

According to our database1, Ming-Jer Kao authored at least 12 papers between 2004 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2015
Set-Triggered-Parallel-Reset Memristor Logic for High-Density Heterogeneous-Integration Friendly Normally Off Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014
ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing.
Proceedings of the Symposium on VLSI Circuits, 2014

A nonvolatile look-up table using ReRAM for reconfigurable logic.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.
IEEE J. Solid State Circuits, 2013

Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2011
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Diagnosis of MRAM Write Disturbance Fault.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Low power design of phase-change memory based on a comprehensive model.
IET Comput. Digit. Tech., 2010

2008
Write Disturbance Modeling and Testing for MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Diagnosis for MRAM write disturbance fault.
Proceedings of the 2007 IEEE International Test Conference, 2007

2006
Testing MRAM for Write Disturbance Fault.
Proceedings of the 2006 IEEE International Test Conference, 2006

2004
MRAM Defect Analysis and Fault Modeli.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004


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