Tuo-Hung Hou

Orcid: 0000-0002-9686-7076

According to our database1, Tuo-Hung Hou authored at least 18 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Two-dimensional materials for artificial synapses: toward a practical application.
Neuromorph. Comput. Eng., 2022

Hardware-Robust In-RRAM-Computing for Object Detection.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

2021
Progress and Benchmark of Spiking Neuron Devices and Circuits.
Adv. Intell. Syst., 2021

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Phase and Carrier Polarity Control of Sputtered MoTe2 by Plasma-induced Defect Engineering.
Proceedings of the 2020 Device Research Conference, 2020

2019
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.
CoRR, 2018

2016
3D resistive RAM cell design for high-density storage class memory - a review.
Sci. China Inf. Sci., 2016

2015
Crossbar array of selector-less TaO<sub>x</sub>/TiO<sub>2</sub> bilayer RRAM.
Microelectron. Reliab., 2015

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2010
Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010


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