Craig R. Walters

According to our database, Craig R. Walters authored at least 12 papers between 2009 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

The IBM Telum II Processor.

Christopher J. Berry, Michael J. Becht, Tim E. Bubb, Howard Haynie, Robert J. Sonnelitter, Katie Seggerman, Jonathan Hsieh, Edward Malley, Mike Cadigan, Susan M. Eickhoff, Matthias Klein, Craig R. Walters, Christian G. Zoellin, Cédric Lichtenau

IEEE Micro, 2025

Enterprise Class Modular Cache Hierarchy.

Craig R. Walters, Deanna Postles Dunn Berger, Robert J. Sonnelitter, Alper Buyuktosunoglu

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

2024

IBM z16 Modular Scalable Cache Hierarchy and Future Concept Applications.

Craig R. Walters

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Enterprise-Class Cache Compression Design.

Alper Buyuktosunoglu, David Trilla, Bülent Abali, Deanna Postles Dunn Berger, Craig R. Walters, Jang-Soo Lee

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023

Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability.

Deanna Postles Dunn Berger, Christian Jacobi, Craig R. Walters, Robert J. Sonnelitter, Mike Cadigan, Matthias Klein

IEEE Micro, 2023

2020

Design of the IBM z15 microprocessor.

Anthony Saporito, Martin Recktenwald, Christian Jacobi, Gerrit Koch, Deanna Postles Dunn Berger, Robert J. Sonnelitter, Craig R. Walters, Jang-Soo Lee, Cédric Lichtenau, Ulrich Mayer, Eduard Herkel, Stefan Payer, Silvia M. Müller, Vesselina K. Papazova, Ekaterina M. Ambroladze, Timothy C. Bronson

IBM J. Res. Dev., 2020

2018

Performance innovations in the IBM z14 platform.

Craig R. Walters, David S. Hutton, Edward W. Chencinski, Christine Axnix, Ralf Winkelmann, Michael F. Fee, Anthony Saporito, Christian Jacobi

IBM J. Res. Dev., 2018

2015

The IBM z13 processor cache subsystem.

Craig R. Walters, Pak-kin Mak, Deanna Postles Dunn Berger, Michael A. Blake, Tim Bronson, K. D. Klapproth, A. J. O'Neill, Robert J. Sonnelitter, Vesselina K. Papazova

IBM J. Res. Dev., 2015

2012

Performance innovation in the IBM zEnterprise 196 processor.

Dan F. Greiner, Marcel M. Mitran, Timothy J. Slegel, Craig R. Walters, Charles F. Webb

IBM J. Res. Dev., 2012

IBM zEnterprise 196 microprocessor and cache subsystem.

Fadi Busaba, Michael A. Blake, Brian W. Curran, Michael F. Fee, Christian Jacobi, Pak-kin Mak, Brian R. Prasky, Craig R. Walters

IBM J. Res. Dev., 2012

2009

IBM System z10 processor cache subsystem microarchitecture.

Pak-kin Mak, Craig R. Walters, Gary E. Strait

IBM J. Res. Dev., 2009

IBM System z10 I/O subsystem.

Edward W. Chencinski, M. A. Check, Casimer M. DeCusatis, H. Deng, M. Grassi, Thomas A. Gregg, Markus M. Helms, A. D. Koenig, L. Mohr, Kulwant M. Pandey, Thomas Schlipf, Torsten Schober, H. Ulrich, Craig R. Walters

IBM J. Res. Dev., 2009