Christian G. Zoellin

According to our database1, Christian G. Zoellin authored at least 23 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021

2018
New database compression assists in the IBM z14 processor.
IBM J. Res. Dev., 2018

Enabling pervasive encryption through IBM Z stack innovations.
IBM J. Res. Dev., 2018


2017
Static netlist verification for IBM high-frequency processors using a tree-grammar.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2015
Test planning for low-power built-in self test.
PhD thesis, 2015

2011
Efficient multi-level fault simulation of HW/SW systems for structural faults.
Sci. China Inf. Sci., 2011

2010
Efficient Concurrent Self-Test with Partially Specified Patterns.
J. Electron. Test., 2010

Low-power test planning for arbitrary at-speed delay-test clock schemes.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

System reliability evaluation using concurrent multi-level simulation of structural faults.
Proceedings of the 2011 IEEE International Test Conference, 2010

Efficient fault simulation on many-core processors.
Proceedings of the 47th Design Automation Conference, 2010

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead.
Proceedings of the 14th IEEE European Test Symposium, 2009

Test exploration and validation using transaction level models.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Integrating Scan Design and Soft Error Correction in Low-Power Applications.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Selective Hardening in Early Design Steps.
Proceedings of the 13th European Test Symposium, 2008

Test Set Stripping Limiting the Maximum Number of Specified Bits.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Scan chain clustering for test power reduction.
Proceedings of the 45th Design Automation Conference, 2008

2007
Programmable deterministic Built-In Self-Test.
Proceedings of the 2007 IEEE International Test Conference, 2007

A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Scan Test Planning for Power Reduction.
Proceedings of the 44th Design Automation Conference, 2007

2006
BIST Power Reduction Using Scan-Chain Disable in the Cell Processor.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
Blue Gene/L compute chip: Synthesis, timing, and physical design.
IBM J. Res. Dev., 2005


  Loading...