Crispín Gómez Requena

ACM Trans. Archit. Code Optim., 2019

2018

Efficient selective multicore prefetching under limited memory bandwidth.

[BibT_eX]

[DOI]

Vicent Selfa

J. Parallel Distributed Comput., 2018

2017

XOR-based HoL-blocking reduction routing mechanisms for direct networks.

[BibT_eX]

[DOI]

Parallel Comput., 2017

2016

A Family of Fault-Tolerant Efficient Indirect Topologies.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

The k-ary n-direct s-indirect family of topologies for large-scale interconnection networks.

[BibT_eX]

[DOI]

J. Supercomput., 2016

A Simple Activation/Deactivation Prefetching Scheme for Chip Multiprocessors.

[BibT_eX]

[DOI]

Vicent Selfa

Proceedings of the 24th Euromicro International Conference on Parallel, 2016

2015

A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies.

[BibT_eX]

[DOI]

J. Supercomput., 2015

Bringing real processors to labs.

[BibT_eX]

[DOI]

Comput. Appl. Eng. Educ., 2015

Methodologies and Performance Metrics to Evaluate Multiprogram Workloads.

[BibT_eX]

[DOI]

Vicent Selfa

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

XORAdap: A HoL-Blocking Aware Adaptive Routing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Row Tables: Design Choices to Exploit Bank Locality in Multiprogram Workloads.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Speeding-up the fault-tolerance analysis of interconnection networks.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015

2014

FT-RUFT: A Performance and Fault-Tolerant Efficient Indirect Topology.

[BibT_eX]

[DOI]

Roberto Peñaranda Cebrian

Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

HoL-Blocking Avoidance Routing Algorithms in Direct Topologies.

[BibT_eX]

[DOI]

María Engracia Gómez Requena

Jesús Escudero-Sahuquillo

José Duato Marín

Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Combining HoL-blocking avoidance and differentiated services in high-speed interconnects.

[BibT_eX]

[DOI]

Pedro Yébenes

Proceedings of the 21st International Conference on High Performance Computing, 2014

2013

A New Methodology for Studying Realistic Processors in Computer Science Degrees.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Deterministic Routing with HoL-Blocking-Awareness for Direct Topologies.

[BibT_eX]

[DOI]

Jesús Escudero-Sahuquillo

Proceedings of the International Conference on Computational Science, 2013

BBQ: A Straightforward Queuing Scheme to Reduce HoL-Blocking in High-Performance Hybrid Networks.

[BibT_eX]

[DOI]

Pedro Yebenes Segura

Pedro Javier García

Francisco J. Quiles

Proceedings of the Euro-Par 2013 Parallel Processing, 2013

Impact of the Memory Controller on the Performance of Parallel Workloads.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

2012

A New Family of Hybrid Topologies for Large-Scale Interconnection Networks.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Symposium on Network Computing and Applications, 2012

IODET: A HoL-blocking-aware Deterministic Routing Algorithm for Direct Topologies.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

Towards an Efficient Fat-Tree like Topology.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

2011

How to reduce packet dropping in a bufferless NoC.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2011

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.

[BibT_eX]

[DOI]

Alessandro Strano

Proceedings of the Design, Automation and Test in Europe, 2011

2009

FT<sup>2</sup>EI: A Dynamic Fault-Tolerant Routing Methodology for Fat Trees with Exclusion Intervals.

[BibT_eX]

[DOI]

María Engracia Gómez Requena

J. F. D. Marin

IEEE Trans. Parallel Distributed Syst., 2009

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.

[BibT_eX]

[DOI]

Daniele Ludovici

Simone Medardoni

Georgi Nedeltchev Gaydadjiev

Davide Bertozzi

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Beyond Fat-tree: Unidirectional Load--Balanced Multistage Interconnection Network.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2008

Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity.

[BibT_eX]

[DOI]

Proceedings of the 16th Euromicro International Conference on Parallel, 2008

RUFT: Simplifying the Fat-Tree Topology.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008

An Efficient Switching Technique for NoCs with Reduced Buffer Requirements.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008

Reducing Packet Dropping in a Bufferless NoC.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2008, 2008

2007

An Efficient Fault-Tolerant Routing Methodology for Fat-Tree Interconnection Networks.

[BibT_eX]

[DOI]

Proceedings of the Parallel and Distributed Processing and Applications, 2007

Deterministic versus Adaptive Routing in Fat-Trees.

[BibT_eX]

[DOI]