María Engracia Gómez

Affiliations:
  • Polytechnic University of Valencia, Spain


According to our database1, María Engracia Gómez authored at least 86 papers between 1999 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Effect of Hyper-Threading in Latency-Critical Multithreaded Cloud Applications and Utilization Analysis of the Major System Resources.
Future Gener. Comput. Syst., 2022

A Neural Network to Estimate Isolated Performance from Multi-Program Execution.
Proceedings of the 30th Euromicro International Conference on Parallel, 2022

2021
Segment Switching: A New Switching Strategy for Optical HPC Networks.
IEEE Access, 2021

2020
Bandwidth-Aware Dynamic Prefetch Configuration for IBM POWER8.
IEEE Trans. Parallel Distributed Syst., 2020

An efficient cache flat storage organization for multithreaded workloads for low power processors.
Future Gener. Comput. Syst., 2020

Understanding Cloud Workloads Performance in a Production like Environment.
CoRR, 2020

Impact of the Array Shape and Memory Bandwidth on the Execution Time of CNN Systolic Arrays.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
FOS: a low-power cache organization for multicores.
J. Supercomput., 2019

Modeling and analysis of the performance of exascale photonic networks.
Concurr. Comput. Pract. Exp., 2019

2018
TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction.
IEEE Trans. Parallel Distributed Syst., 2018

Efficient selective multicore prefetching under limited memory bandwidth.
J. Parallel Distributed Comput., 2018

Workload Characterization for Exascale Computing Networks.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

2017
A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches.
IEEE Trans. Parallel Distributed Syst., 2017

TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs.
IEEE Trans. Parallel Distributed Syst., 2017

XOR-based HoL-blocking reduction routing mechanisms for direct networks.
Parallel Comput., 2017

The Tag Filter Architecture: An energy-efficient cache and directory design.
J. Parallel Distributed Comput., 2017

A research-oriented course on Advanced Multicore Architecture: Contents and active learning methodologies.
J. Parallel Distributed Comput., 2017

A fault-tolerant routing strategy for <i>k</i>-ary <i>n</i>-direct <i>s</i>-indirect topologies based on intermediate nodes.
Concurr. Comput. Pract. Exp., 2017

Modeling a Photonic Network for Exascale Computing.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
A Family of Fault-Tolerant Efficient Indirect Topologies.
IEEE Trans. Parallel Distributed Syst., 2016

Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2016

The k-ary n-direct s-indirect family of topologies for large-scale interconnection networks.
J. Supercomput., 2016

A Simple Activation/Deactivation Prefetching Scheme for Chip Multiprocessors.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Accurately modeling a photonic NoC in a detailed CMP simulation framework.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

TokenTLB: A Token-Based Page Classification Approach.
Proceedings of the 2016 International Conference on Supercomputing, 2016

A New Fault-Tolerant Routing Methodology for KNS Topologies.
Proceedings of the 2nd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era HiPINEB@HPCA 2016, 2016

A Directory Cache with Dynamic Private-Shared Partitioning.
Proceedings of the 23rd IEEE International Conference on High Performance Computing, 2016

Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
PS directory: a scalable multilevel directory cache for CMPs.
J. Supercomput., 2015

PS-Cache: an energy-efficient cache design for chip multiprocessors.
J. Supercomput., 2015

A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies.
J. Supercomput., 2015

Bringing real processors to labs.
Comput. Appl. Eng. Educ., 2015

The Tag Filter Cache: An Energy-Efficient Approach.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Methodologies and Performance Metrics to Evaluate Multiprogram Workloads.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

XORAdap: A HoL-Blocking Aware Adaptive Routing Algorithm.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Row Tables: Design Choices to Exploit Bank Locality in Multiprogram Workloads.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

A Research-Oriented Course on Advanced Multicore Architecture.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Speeding-up the fault-tolerance analysis of interconnection networks.
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015

2014
FT-RUFT: A Performance and Fault-Tolerant Efficient Indirect Topology.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

HoL-Blocking Avoidance Routing Algorithms in Direct Topologies.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2013
Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks.
IEEE Trans. Computers, 2013

A New Methodology for Studying Realistic Processors in Computer Science Degrees.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

Deterministic Routing with HoL-Blocking-Awareness for Direct Topologies.
Proceedings of the International Conference on Computational Science, 2013

Exploiting Parallelization on Address Translation: Shared Page Walk Cache.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

2012
Extending Magny-Cours Cache Coherence.
IEEE Trans. Computers, 2012

A New Family of Hybrid Topologies for Large-Scale Interconnection Networks.
Proceedings of the 11th IEEE International Symposium on Network Computing and Applications, 2012

Cache Miss Characterization in Hierarchical Large-Scale Cache-Coherent Systems.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

IODET: A HoL-blocking-aware Deterministic Routing Algorithm for Direct Topologies.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

OMHI 2012: First International Workshop on On-chip Memory Hierarchies and Interconnects: Organization, Management and Implementation.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

Towards an Efficient Fat-Tree like Topology.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

Detecting Sharing Patterns in Industrial Parallel Applications for Embedded Heterogeneous Multicore Systems.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

PS-Dir: a scalable two-level directory cache.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Networks, Fault-Tolerant.
Proceedings of the Encyclopedia of Parallel Computing, 2011

How to reduce packet dropping in a bufferless NoC.
Concurr. Comput. Pract. Exp., 2011

Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip.
Proceedings of the NOCS 2010, 2010

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

EMC<sup>2</sup>: Extending Magny-Cours coherence for large-scale servers.
Proceedings of the 2010 International Conference on High Performance Computing, 2010

2009
FT<sup>2</sup>EI: A Dynamic Fault-Tolerant Routing Methodology for Fat Trees with Exclusion Intervals.
IEEE Trans. Parallel Distributed Syst., 2009

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Beyond Fat-tree: Unidirectional Load--Balanced Multistage Interconnection Network.
IEEE Comput. Archit. Lett., 2008

Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity.
Proceedings of the 16th Euromicro International Conference on Parallel, 2008

Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

RUFT: Simplifying the Fat-Tree Topology.
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008

An Efficient Switching Technique for NoCs with Reduced Buffer Requirements.
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008

Reducing Packet Dropping in a Bufferless NoC.
Proceedings of the Euro-Par 2008, 2008

2007
An Efficient Fault-Tolerant Routing Methodology for Fat-Tree Interconnection Networks.
Proceedings of the Parallel and Distributed Processing and Applications, 2007

Deterministic versus Adaptive Routing in Fat-Trees.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
A Routing Methodology for Achieving Fault Tolerance in Direct Networks.
IEEE Trans. Computers, 2006

An Efficient Fault-Tolerant Routing Strategy for Tori and Meshes.
Scalable Comput. Pract. Exp., 2006

FIR: An efficient routing strategy for tori and meshes.
J. Parallel Distributed Comput., 2006

On the Influence of the Selection Function on the Performance of Fat-Trees.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

2005
A Memory-Effective Fault-Tolerant Routing Strategy for Direct Interconnection Networks.
Proceedings of the 4th International Symposium on Parallel and Distributed Computing (ISPDC 2005), 2005

A Memory-Effective Routing Strategy for Regular Interconnection Networks.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori.
IEEE Comput. Archit. Lett., 2004

A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2004

An Effective Fault-Tolerant Routing Methodology for Direct Networks.
Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004

A New Adaptive Fault-Tolerant Routing Methodology for Direct Networks.
Proceedings of the High Performance Computing, 2004

2003
VOQSW: A Methodology to Reduce HOL Blocking in InfiniBand Networks.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Evaluation of Routing Algorithms for InfiniBand Networks (Research Note).
Proceedings of the Euro-Par 2002, 2002

2000
A New Approach in the Modeling and Generation of Synthetic Disk Workload.
Proceedings of the MASCOTS 2000, Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 29 August, 2000

A new approach in the analysis and modeling of disk access patterns.
Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

1999
Analysis of Self-Similarity in I/O Workload Using Structural Modeling.
Proceedings of the MASCOTS 1999, 1999


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