Simone Medardoni

According to our database1, Simone Medardoni authored at least 15 papers between 2007 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip.
Proceedings of the NOCS 2010, 2010

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing.
Proceedings of the NOCS 2010, 2010

2009
Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip.
PhD thesis, 2009

Efficient implementation of distributed routing algorithms for NoCs.
IET Comput. Digit. Tech., 2009

Flexible DOR routing for virtualization of multicore chips.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Yield-oriented evaluation methodology of network-on-chip routing implementations.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
Proceedings of the Design, Automation and Test in Europe, 2009

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.
Proceedings of the 2009 International Conference on Complex, 2009

2008
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Network Interface Sharing Techniques for Area Optimized NoC Architectures.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Variation tolerant NoC design by means of self-calibrating links.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Control and datapath decoupling in the design of a NoC switch: area, power and performance implications.
Proceedings of the International Symposium on System-on-Chip, 2007

Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007


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