Daniele Ludovici
According to our database1,
Daniele Ludovici
authored at least 16 papers
between 2004 and 2013.
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Bibliography
2013
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs.
ACM Trans. Embed. Comput. Syst., 2013
2012
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012
2011
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011
Proceedings of the 2011 International Symposium on System on Chip, 2011
Proceedings of the Fifth International Workshop on Interconnection Network Architecture, 2011
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
Proceedings of the Design, Automation and Test in Europe, 2009
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.
Proceedings of the 2009 International Conference on Complex, 2009
2004
On the maximum achievable rates in wireless meshed networks: centralized versus decentralized solutions.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004