Paul Wielage

According to our database, Paul Wielage authored at least 13 papers between 2001 and 2017.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2017

5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter.

Fred Mostert, Daniël Schinkel, Wouter Groothedde, Lucien J. Breems, Remko van Heeswijk, Marto-Jan Koerts, Eric van Iersel, Daniel Groeneveld, Gertjan van Holland, Patrick Zeelen, Derk-Jan Hissink, Martin Pos, Paul Wielage, Fre Jorritsma, Marc Klein Middelink

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2008

Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis.

Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Bart Vermeulen, Marc J. M. Heijligers

IEEE J. Solid State Circuits, 2008

2007

XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis.

Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Marc J. M. Heijligers

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Design and DfT of a high-speed area-efficient embedded asynchronous FIFO.

Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Test quality analysis and improvement for an embedded asynchronous FIFO.

Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005

An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration.

Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees Goossens

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004

An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.

Andrei Radulescu, John Dielissen, Kees Goossens, Edwin Rijpkema, Paul Wielage

Proceedings of the 2004 Design, 2004

2003

Clock synchronization through handshake signalling.

Joep L. W. Kessels, Ad M. G. Peeters, Paul Wielage, Suk-Jin Kim

Microprocess. Microsystems, 2003

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.

Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, Erwin Waterlander

Proceedings of the 2003 Design, 2003

Guaranteeing the Quality of Services in Networks on Chip.

Kees Goossens, John Dielissen, Jef L. van Meerbergen, Peter Poplavko, Andrei Radulescu, Edwin Rijpkema, Erwin Waterlander, Paul Wielage

Proceedings of the Networks on Chip, 2003

2002

Networks on Silicon: Blessing or Nightmare?

Paul Wielage, Kees Goossens

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Networks on Silicon: Combining Best-Effort and Guaranteed Services.

Kees Goossens, Paul Wielage, Ad M. G. Peeters, Jef L. van Meerbergen

Proceedings of the 2002 Design, 2002

2001

Xetal: a low-power high-performance smart camera processor.

Richard P. Kleihorst, Anteneh A. Abbo, André van der Avoird, M. Op de Beeck, Leo Sevat, Paul Wielage, R. van Veen, H. van Herten

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001