DanYu Wu

Orcid: 0009-0000-9595-0348

According to our database¹, DanYu Wu authored at least 23 papers between 2014 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2025

A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., May, 2025

A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., April, 2025

2024

A 16-Bit 5 GS/s DAC With Redundant-MSB-Based Digital Pre-Distortion Achieving SFDR >61 dBc Up to 2.4 GHz in 40-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, December, 2024

A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., September, 2024

A wideband front-end with integrated high-voltage assisted input buffer for high-speed ADC.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2024

2023

A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

A 64Gbps 1.36 Vppd 1.44pJ/b Fully CMOS-Style Transmitter with Active Hybrid Driver in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2021

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 47th ESSCIRC 2021, 2021

A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency.

[BibT_eX]

[DOI]

Proceedings of the 47th ESSCIRC 2021, 2021

2020

Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

100 Gb/s (4 × 25 Gb/s) real-time coherent UDWDM-PON with a large power budget.

[BibT_eX]

[DOI]

JOCN, 2020

2019

An 8 GSps 14 bit RF DAC With IM3<-62 dBc up to 3.6 GHz.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

Demonstration of Bidirectional Real-Time 100 Gb/s (4×25 Gb/s) Coherent UDWDM-PON with Power Budget of 44 dB.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

A 10-GS/s 8-bit SiGe ADC with Isolated 4×4 Analog Input Multiplexer.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2017

A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A four-channel time-interleaved 30-GS/s 6-bit ADC in 0.18 μm SiGe BiCMOS technology.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2017

2016

A 30Gsps 6bit DAC in SiGe BiCMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2014

A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2014

DanYu Wu

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...