Rahul Dilip Limaye

According to our database, Rahul Dilip Limaye authored at least 5 papers between 2004 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver.

Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Khoa Minh Nguyen, Hyung-Jin Lee, Ashoke Ravi, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Satish Venkatesan, Durgesh Srivastava, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Sunder Ramamurthy, Raj Yavatkar, Krishnamurthy Soumyanath

IEEE J. Solid State Circuits, 2013

2012

32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver.

Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Durgesh Srivastava, Satish Venkatesan, Hyung-Jin Lee, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Krishnamurthy Soumyanath, Sunder Ramamurthy

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2007

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.

Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora

IEEE J. Solid State Circuits, 2007

2006

Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache.

Simon Tam, Justin Leung, Rahul Dilip Limaye, Sam Choy, Sujal Vora, Mitsuhiro Adachi

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004

Clock generation and distribution for the 130-nm Itanium^® 2 processor with 6-MB on-die L3 cache.

Simon Tam, Rahul Dilip Limaye, Utpal Nagarji Desai

IEEE J. Solid State Circuits, 2004