Shenggao Li

Orcid: 0000-0001-9296-1121

Affiliations:

Taiwan Semiconductor Manufacturing Company (TSMC), San Jose, CA, USA
Ohio State University, Columbus, OH, USA (PhD 2000)

According to our database¹, Shenggao Li authored at least 17 papers between 1999 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

8.2 A 32Gb/s 12.35Tb/s/mm<sup>2</sup> 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

Fast and Accurate Jitter Amplification Modeling With Variable Pulse Width Response for Statistical BER Analysis in Chiplet Interconnects and Beyond.

[BibT_eX]

[DOI]

Shenggao Li

Maher Amer

IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2025

TSMC in the Silicon Photonics Era - an Electrical Perspective.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2025

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

A 0.296pJ/bit 17.9Tb/s/mm<sup>2</sup> Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022

Interconnect in the Era of 3DIC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2018

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2015

A 22 nm 15-Core Enterprise Xeon® Processor Family.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

2014

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011

Clock generation for a 32nm server processor with scalable cores.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2003

A 10-GHz CMOS quadrature LC-VCO for multirate optical applications.

[BibT_eX]

[DOI]

Shenggao Li

Issy Kipnis

Mohammed Ismail

IEEE J. Solid State Circuits, 2003

1999

The Implementation of a VHDL-AMS to SPICE Converter.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1999

A Lower Power CMOS Micromixer for GHz Wireless Applications.

[BibT_eX]

Proceedings of the VLSI: Systems on a Chip, 1999

Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application.

[BibT_eX]

Proceedings of the VLSI: Systems on a Chip, 1999

Shenggao Li

Timeline

Legend:

Links

Online presence:

On csauthors.net:

Bibliography

Loading...