David E. Schimmel

According to our database1, David E. Schimmel
  • authored at least 26 papers between 1993 and 2006.
  • has a "Dijkstra number"2 of four.

Timeline

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Links

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Bibliography

2006
An asynchronous architecture for modeling intersegmental neural communication.
IEEE Trans. VLSI Syst., 2006

Modeling the data-dependent performance of pattern-matching architectures.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2004
Scalable Pattern Matching for High Speed Networks.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
Energy-Efficient Network Memory for Ubiquitous Devices.
IEEE Micro, 2003

A pattern-matching co-processor for network intrusion detection systems.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Efficient Reconfigurable Logic Circuits for Matching Complex Network Intrusion Detection Patterns.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
TCP-Stream Reassembly and State Tracking in Hardware.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

1998
Guest Editors' Introduction: Early Modeling and Analysis of Packaged Systems.
IEEE Design & Test of Computers, 1998

Hiding Communication Latency in Data Parallel Applications.
IPPS/SPDP, 1998

1997
Performance modeling of dense Cholesky factorization on the MasPar MP-2.
Concurrency - Practice and Experience, 1997

Power/Performance Trade-offs for Direct Networks.
Proceedings of the Parallel Computer Routing and Communication, 1997

CCSIMD: A Concurrent Communication and Computation Framework for SIMD Machines.
Proceedings of the Parallel Computer Routing and Communication, 1997

Power Constrained Design of Multiprocessor Interconnection Networks.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

A VLSI Architecture for Modeling Intersegmental Coordination.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1996
Issues in the Design of High Performance SIMD Architectures.
IEEE Trans. Parallel Distrib. Syst., 1996

Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks.
IEEE Trans. Computers, 1996

Improving Memory Performance for Indirect Accesses on SIMD Computers.
Proceedings of IPPS '96, 1996

Incorporating Multi-Chip Module Packaging Constraints into System Design.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Architectural support for inter-stream communication in an MSIMD system.
Future Generation Comp. Syst., 1995

A Novel Low-Cost Approach to MCM Interconnect Test.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

The impact of pipelining on SIMD architectures.
Proceedings of IPPS '95, 1995

Architectural Support for Inter-Stream Communication in a MSIMD System.
Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

1994
Simulation of Marked Graphs on SIMD Architectures Using Efficient Memory Management.
Proceedings of the MASCOTS '94, Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems, January 31, 1994

A Methodology for Generation and Collection of Multiprocessor Traces.
Proceedings of the MASCOTS '94, Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems, January 31, 1994

Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1993
Analysis of Control Parallelism in SIMD Instruction Streams.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993


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