Madhavan Swaminathan

Orcid: 0000-0003-1729-2807

Affiliations:
  • Georgia Institute of Technology, Atlanta GA, USA


According to our database1, Madhavan Swaminathan authored at least 75 papers between 1995 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2006, "For contributions in design tools, design methodologies and electromagnetic interference (EMI) control for power delivery in digital and mixed signal systems.".

Timeline

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Bibliography

2024
A PPA Study for Heterogeneous 3-D IC Options: Monolithic, Hybrid Bonding, and Microbumping.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024

Design Considerations for DC-DC Voltage Regulators in Distributed Vertical Power Delivery Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Ultra-Wide Bandwidth Substrate Integrated Waveguide Fed Vivaldi Antenna in D-Band Using Glass Interposer.
Proceedings of the IEEE Radio and Wireless Symposium, 2023

Chip-embedded Glass Interposer for 5G Applications.
Proceedings of the IEEE Radio and Wireless Symposium, 2023

Design and Characterization of Bandpass Filter with Multiple Zeros on Glass Interposer for 6G Applications.
Proceedings of the IEEE Radio and Wireless Symposium, 2023

2022
Invertible Neural Networks for Design of Broadband Active Mixers.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

2021
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Design Space Extrapolation for Power Delivery Networks using a Transposed Convolutional Net.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
A Bit-Time-Dependent Model of I/O Drivers for Overclocking Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Behavioral Modeling of Tunable I/O Drivers With Preemphasis Including Power Supply Noise.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.
IEEE Trans. Very Large Scale Integr. Syst., 2020

An Inductive Voltage Regulator With Overdrive Tracking Across Input Voltage in Cascoded Power Stage.
IEEE Trans. Circuits Syst., 2020

Computation of Maximum Voltage Droop in Power Delivery Networks.
IEEE Access, 2020

Determining worst-case eye height in low BER channels using Bayesian optimization.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
Heterogeneous integration for artificial intelligence: Challenges and opportunities.
IBM J. Res. Dev., 2019

Repeater Insertion to Reduce Delay and Power in Copper and Carbon Nanotube-Based Nanointerconnects.
IEEE Access, 2019

Modeling of Voltage-Controlled Oscillators Including I/O Behavior Using Augmented Neural Networks.
IEEE Access, 2019

Machine Learning and Uncertainty Quantification for Surrogate Models of Integrated Devices With a Large Number of Parameters.
IEEE Access, 2019

A Hybrid Methodology for Jitter and Eye Estimation in High-Speed Serial Channels Using Polynomial Chaos Surrogate Models.
IEEE Access, 2019

Process Design Kit and Design Automation for Flexible Hybrid Electronics.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Behavioral Modeling of Pre-emphasis Drivers Including Power Supply Noise Using Neural Networks.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Behavioral Modeling of Tunable I/O Drivers with Pre-emphasis Using Neural Networks.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors.
Proceedings of the International Conference on Computer-Aided Design, 2019

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Global Bayesian Optimization Algorithm and Its Application to Integrated System Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Compact Passive Equalizer Design for Differential Channels in TSV-Based 3-D ICs.
IEEE Access, 2018

Modeling and Performance Analysis of Shielded Differential Annular Through-Silicon Via (SD-ATSV) for 3-D ICs.
IEEE Access, 2018

Polynomial Chaos modeling for jitter estimation in high-speed links.
Proceedings of the IEEE International Test Conference, 2018

A 65nm, 1.15-0.15V, 99.99% Current-efficient Digital Low Dropout Regulator with Asynchronous Non-linear Control for Droop Mitigation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Application of Machine Learning for Optimization of 3-D Integrated Circuits and Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Investigation of surface roughness effects for D-band SIW transmission lines on LCP substrate.
Proceedings of the 2017 IEEE Radio and Wireless Symposium, 2017

2015
Lossy frequency selective surfaces for gas sensing using ZnO films.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

2014
Managing signal, power and thermal integrity for 3D integration.
Proceedings of the 2014 International Test Conference, 2014

3D-ICs with self-healing capability for thermal effects in RF circuits.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
Managing signal and power integrity using power transmission lines and alternative signaling schemes.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Do we need wide flits in Networks-on-Chip?
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Electrical and thermal analysis for design exchange formats in three dimensional integrated circuits.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
A New Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A self-testable SiGe LNA and Built-in-Self-Test methodology for multiple performance specifications of RF amplifiers.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

3D transient thermal solver using non-conformal domain decomposition approach.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
Transient Analysis of CMOS-Gate-Driven RLGC Interconnects Based on FDTD.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010
Low-Cost Specification Based Testing of RF Amplifier Circuits using Oscillation Principles.
J. Electron. Test., 2010

2009
Inductance and Resistance Calculations in Three-Dimensional Packaging Using Cylindrical Conduction-Mode Basis Functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Iterative built-in testing and tuning of mixed-signal/RF systems.
Proceedings of the 27th International Conference on Computer Design, 2009

A novel self-healing methodology for RF Amplifier circuits based on oscillation principles.
Proceedings of the Design, Automation and Test in Europe, 2009

Self-Calibrating Embedded RF Down-Conversion Mixers.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Electrical-thermal co-analysis for power delivery networks in 3D system integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Electrical modeling of Through Silicon and Package Vias.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
On-Chip Power-Grid Simulation Using Latency Insertion Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Analytical Stability Condition of the Latency Insertion Method for Nonuniform G<i>LC</i> Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnects.
Proceedings of the 45th Design Automation Conference, 2008

Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM.
Proceedings of the 45th Design Automation Conference, 2008

Load-Board/PCB Noise Suppression via Electromagnetic Band Gap Power Plane Patterning.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Low-Cost One-Port Approach for Testing Integrated RF Substrates.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Analysis for Signal and Power Integrity Using the Multilayered Finite Difference Method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Placement and routing of RF embedded passive designs in LCP substrate.
Proceedings of the 25th International Conference on Computer Design, 2007

Computationally Efficient Power Integrity Simulation for System-on-Package Applications.
Proceedings of the 44th Design Automation Conference, 2007

2006
Enhancement of Signal Integrity and Power Integrity with Embedded Capacitors in High-Speed Packages.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

System level signal and power integrity analysis methodology for system-in-package applications.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Delay extraction from frequency domain data for causal macro-modeling of passive networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Application of Wavelets and Generalized Pencil-Of-Function Method for the Extraction of Noise Current Spectrum and Simulation of Simultaneous Switching Noise.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003
Modeling and Analysis of Power Distribution Networks for Gigabit Applications.
IEEE Trans. Mob. Comput., 2003

Modeling and Analysis of Power Distribution Networks for Gigabit Applications.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Optimal Sequencing Energy Allocation for CMOS Integrated Systems.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000
A Methodology for the Placement and Optimization of Decoupling Capacitors for Gigahertz Systems.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives.
J. VLSI Signal Process., 1999

1998
Fault detection and automated fault diagnosis for embedded integrated electrical passives.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997
A Survey of Test Techniques for MCM Substrates.
J. Electron. Test., 1997

1996
Low-cost diagnosis of defects in MCM substrate interconnections.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995
A Novel Low-Cost Approach to MCM Interconnect Test.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995


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