Pierce Chuang

According to our database1, Pierce Chuang authored at least 37 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Lumos : Empowering Multimodal LLMs with Scene Text Recognition.
CoRR, 2024

Now It Sounds Like You: Learning Personalized Vocabulary On Device.
Proceedings of the AAAI 2024 Spring Symposium Series, 2024

Towards Zero-Shot Multilingual Transfer for Code-Switched Responses.
Proceedings of the 61st Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), 2023

Omni-Sparsity DNN: Fast Sparsity Optimization for On-Device Streaming E2E ASR Via Supernet.
Proceedings of the IEEE International Conference on Acoustics, 2022

Noisy Training Improves E2E ASR for the Edge.
CoRR, 2021

Latency-Aware Neural Architecture Search with Multi-Objective Bayesian Optimization.
CoRR, 2021

Span Pointer Networks for Non-Autoregressive Task-Oriented Semantic Parsing.
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2021, 2021

F-CAD: A Framework to Explore Hardware Accelerators for Codec Avatar Decoding.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Improving Efficiency in Neural Network Accelerator Using Operands Hamming Distance optimization.
CoRR, 2020

One Weight Bitwidth to Rule Them All.
Proceedings of the Computer Vision - ECCV 2020 Workshops, 2020

IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems.
IEEE J. Solid State Circuits, 2019

Accurate and Efficient 2-bit Quantized Neural Networks.
Proceedings of the Second Conference on Machine Learning and Systems, SysML 2019, 2019

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018

IBM z14 design methodology enhancements in the 14-nm technology node.
IBM J. Res. Dev., 2018

Bridging the Accuracy Gap for 2-bit Quantized Neural Networks (QNN).
CoRR, 2018

PACT: Parameterized Clipping Activation for Quantized Neural Networks.
CoRR, 2018

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Viterbi-based Pruning for Sparse Matrix with Fixed and High Index Compression Ratio.
Proceedings of the 6th International Conference on Learning Representations, 2018

Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors.
Proceedings of the 55th Annual Design Automation Conference, 2018

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

26.2 Power supply noise in a 22nm z13™ microprocessor.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Runtime slack-deficit detection for a low-voltage DCT circuit.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

VLSI implementation of high-throughput, low-energy, configurable MIMO detector.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Voltage-Boosted Synchronizers.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Constant Delay Logic Style.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Design and analysis of metastable-hardened flip-flops in sub-threshold region.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Analysis of power supply noise mitigation circuits.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Comparative analysis and study of metastability on high-performance flip-flops.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009