Pierce Chuang
According to our database1,
Pierce Chuang
authored at least 37 papers
between 2009 and 2024.
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Bibliography
2024
2023
Proceedings of the 61st Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), 2023
2022
Omni-Sparsity DNN: Fast Sparsity Optimization for On-Device Streaming E2E ASR Via Supernet.
Proceedings of the IEEE International Conference on Acoustics, 2022
2021
CoRR, 2021
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2021, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Improving Efficiency in Neural Network Accelerator Using Operands Hamming Distance optimization.
CoRR, 2020
Proceedings of the Computer Vision - ECCV 2020 Workshops, 2020
2019
IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems.
IEEE J. Solid State Circuits, 2019
Proceedings of Machine Learning and Systems 2019, 2019
2018
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018
IBM J. Res. Dev., 2018
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the 6th International Conference on Learning Representations, 2018
Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
2014
A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2009
Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009