Davide Medina

According to our database1, Davide Medina authored at least 6 papers between 1990 and 1998.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

1998
Integrating Online and Offline Testing of a Switching Memory.
IEEE Des. Test Comput., 1998

1996
Scan insertion criteria for low design impact.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

A Parametric Design of a Built-in Self-Test FIFO Embedded Memory.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
Industrial BIST of Embedded RAMs.
IEEE Des. Test Comput., 1995

1994
An industrial experience in the built-in self test of embedded RAMs.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

1990
A diagnostic test pattern generation algorithm.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990


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